Address code generation for DSP instruction-set architectures
handle: 10203/3121
Address code generation for DSP instruction-set architectures
This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to the address computation of array accesses. The information is used in generating auto-modification addressing operations provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance and reducing code size.
- Korea Advanced Institute of Science and Technology Korea (Republic of)
- Korean Association Of Science and Technology Studies Korea (Republic of)
- SK Group (United States) United States
- SK Group (South Korea) Korea (Republic of)
- Korea Advanced Institute of Science and Technology Korea (Republic of)
cycle counts, auto-modification addressing, Code size
cycle counts, auto-modification addressing, Code size
5 Research products, page 1 of 1
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