G-helix: lithography-based wafer-level compliant chip-to-substrate interconnects
Authors: Suresh K. Sitaraman; G. Lo;
G-helix: lithography-based wafer-level compliant chip-to-substrate interconnects
Abstract
In this work, the fabrication and the reliability of 100 /spl mu/m pitch compliant off-chip G-helix interconnects are presented. A three-mask process was used to successfully fabricate the free-standing compliant interconnect at a pitch of 100 /spl mu/m. The geometry of the interconnect was optimized for mechanical and electrical performance. Also, a thermo-mechanical reliability simulation was performed. It was seen from the simulations that the G-helix interconnect assembly on an organic substrate, without the use of an underfill, could last more than 1000 thermal cycles.
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- Georgia Institute of Technology United States
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citations
Citations provided by BIP!
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
popularity
Popularity provided by BIP!
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
19
Average
Top 10%
Top 10%
