The performance improvements obtained from the proper implementation of error control codes is one of the key elements that make the difference within competition. The key elements that makes a product successful can be either low complexity, low energy consumption, or low error probability performance. The three companies involved in the NAND project (STMicroelectronics, Thales and TurboConcept) are already present on several markets involving architecture of error control codes. The three companies are willing to exploit new disruptive technologies for commercial use of error control codes in both point to point and broadcast wireless communications. In parallel to these industrial needs, several scientists have recently tackled the performance evaluation of iterative decoders in stochastic architectures. In the next generation of integrated circuits with transistor sizes below 40 nm, every single gate may sometimes output a wrong value due to transient defects. One of the first proposed trends has been to evaluate, both theoretically and practically, the performance degradation induced by a stochastic architecture, then using wisely redundancy to reduce the negative effects introduced by the transistor noise. Through these research endeavors, an unexpected spin-off was identified: the noise inside the decoders is not necessarily an enemy to combat, but it can be used as an ally. Indeed, recent works have shown that the controlled injection of noise in an iterative error control decoder can significantly enhance the error correction performance, and thus, contribute to mitigate the effect of the transmission channel perturbations. In other words, and even if it may appear as a paradox at first glance, noise in an iterative decoder can help to combat channel noise! In this context, the NAND project will allow both academic and industrial partners to share a common objective: the design of high-performance and low-complexity error control codes that rely on this disruptive decoding technique in order to develop differentiated products and thus increase the French industry competitiveness. The consortium will analyze, both from theoretical and practical points of view, the performance gains that can be obtained from introducing some noise in iterative LDPC and Turbo decoders. The consortium targets significant performance gains, both in the convergence domain (a fraction of dB in Signal to Noise ratio) and in the error floor region (several orders of magnitude for a given Signal to Noise ratio). To carry out this project, all the aspects of the problem will be considered. From a theoretical point of view, the asymptotic performance of noisy decoders will be analyzed, in order to improve the performance in the convergence domain. The error floor performance analysis will consist on identifying the topological structures that might prevent the decoder to converge. We will study how noise can help iterative decoders to avoid this harmful topological structures. Fast simulation tools will be developed on parallel programmable architectures to confirm experimentally the theoretical analysis. Novel iterative decoder architectures will be proposed to take into account digital noise generation and injection in the decoding process. A more prospective analysis will be carried out for analog noise generation. As a proof of concept, two demonstrators (LDPC and Turbo-Code) will be implemented on FPGA boards. Finally, the NAND decoders will be incorporated into simulation chains, in order to measure their performance for non-Gaussian channels that are considered in several applications targeted by the three industrial partners (aeronautic mono-carrier channels, modulation with high number of states, fading channels, satellite channels with non-linear distortion).