Critical embedded systems are subject to time and security guarantee requirements, while requiring significant computing power that can only be offered by multicore processors. Off-the-shelf processors meet the performance requirements but do not provide the necessary safety and security guarantees, on the one hand because they were not necessarily designed for this purpose, and on the other hand because the details of their internal architecture are not known, thus prohibiting any reliable analysis of their behavior. The aim of the project is to propose a multicore processor that meets these two requirements. The availability and control of a safe (temporally predictable) and secure processor will allow a state and its public and private actors to carry out their missions in optimal conditions of trust. We will follow the path of the open hardware movement which offers the possibility to develop specific processors. The design of a specific processor enabled by the technological, software and organizational infrastructure of the RISC-V ecosystem meets the challenges of sovereignty by (1) ensuring components availability and (2) guaranteeing complete control of the hardware architecture. This full knowledge will enable the relevant implementation of formal verification tools for the expected properties in terms of predictability and security (complete and precise knowledge of the hardware implementation is the guarantee of being able to produce a correct model). Moreover, it will also make it possible to verify the authenticity and fidelity of the components.