Nowadays, the nanoelectronics market is dominated by mobile applications for which ultra-low operating power (LOP) devices are required. Hence, the research efforts are devoted not so much to increase the electrical performance of the single processor, which can be achieved by using an aggressive core parallelization, but rather to decrease the supply voltage VDD. Since the dynamic power consumption depends on VDD2, large benefits could be obtained by finding new device architectures and materials allowing circuits to work with reduced supply voltages. However, many technological and theoretical issues have to be addressed in order to open the way towards the design optimization of device architectures and materials for low-operating power applications. NOODLES goal is to develop predictive multi-scale simulations and efficient semi-analytical models ranging from full-quantum to semi-classical approaches, capable to identify the optimal choice of device architecture (nanowires, FinFETs, FDSOI), channel material (sSi, SiGe, III-V) and device operating principle (MOSFET, Tunnel-FET) in terms of the best electrical performance/consumption trade-off. In order to achieve this ambitious objective, NOODLES will explore the main physical mechanisms determining the properties of nanodevices for ultra-LOP applications. Such simulations have to be based on improved physical models able to reliably describe realistic devices. Therefore, NOODLES focus will be on the following problems: (i) the evaluation of self-heating effects and hot-carrier transport, which can be particularly detrimental in miniaturized nanostructures such as NWs, FinFETs and FDSOI; (ii) the realistic description of extra-channel parasitic effects such as access resistances and capacitances, which are as important as the channel region in determining the behavior of circuits based on short-channel devices, but have been neglected in most quantum simulations up to now; (iii) the assessment of III-V semiconductors as alternative materials to Si in both MOSFETs and Tunnel-FETs, which can indeed boost the electrical performance thanks to their high mobility and bandstructure properties. This project involves six partners who already worked together in a previous successful project founded by the ANR in 2010 (QUASANOVA). The partnership gathers the complementary expertise that is necessary to achieve NOODLES goals. In particular they have a strong track record in atomistic simulations of carrier transport, in 3D full-quantum self-consistent simulation of nanodevices, in advanced TCAD simulations and in analytical equations exploited to simulate benchmark circuits as the ring oscillator.