Most of optical transmission systems now deployed use 10Gb/s signals associated with wavelength division multiplexing (WDM) technology. In 2005, Infinera introduced photonic integrated circuits (PIC) on InP and designed a device with 10 wavelengths at 10Gb/s on a single chip. A promising alternative to push integration of photonic circuits even further is to rely on silicon photonics. Silicon photonics will later allow the joint integration of high speed electronics with photonics on the same chip. ULTIMATE proposes to demonstrate a 4x100Gb/s PIC transmitter based on this technology, integrating 4 transmitters at 100Gb/s, namely 4 tunable lasers, 8 QPSK modulators and semiconductor optical amplifiers (SOA). This PIC will leverage the lessons learned from Alcatel-Lucent’s coherent solution at 100Gb/s using PDM QPSK modulation format and coherent detection, the first of its kind on the market since mid 2010, and from pioneer work on Silicon Photonics achieved by the consortium. A first technical challenge concerns the optical laser sources. Compared to first demonstration done by III-Vlab and CEA within HELIOS FP7 project, the objectives are to increase output power and to demonstrate tunability over 30nm while achieving narrow linewidth for compatibility with coherent detection. A second challenge deals with high speed optical modulator. Modulator bandwidth should be increased compared to first demonstration done by IEF within HELIOS FP7 project, structure should be more complex (QPSK modulator) and modulator should be compatible with low output voltage coming from CMOS chip. Several iterations will be required to fully achieve these ambitious objectives. The project will be split in three phases. Phase one will demonstrate tunable laser on one hand and high bandwidth BPSK modulator as well as QPSK modulator on the other one. Phase two will demonstrate the integration of one tunable laser with two QPSK modulators and SOAs to demonstrate a first 100Gb/s transmitter. Optimized packaging will be realized as well as system validation in a WDM test bed. Phase three will integrate four transmitters (but only one transmitter packaged with RF lines) and will benefit from lessons learned in phase 1 and 2. Transmitter and high speed CMOS FPGA will be soldered on a printed circuit board for system tests. Indeed, a longer term challenge, not within the frame of this project, will be to integrate on a single chip a high speed CMOS circuit generating several 25Gb/s streams and the photonic part including laser, modulator and SOA. An optimized packaging is also required to fully exploit silicon photonic chip performance in a system test bed. The objective here is to demonstrate optical transmission over distances larger than 1000 km in wavelength division multiplexing (WDM) context. Photonic integration is a key method to reduce cost, footprint and power consumption of optical transmission systems. It will bring an extremely valuable differentiator to WDM system vendors having access to such technologies. Integration of several 100Gb/s wavelengths on a single chip appears today’s as one of the most promising direction to answer future market requirements for 400Gb/s or 1Tb/s. While MICROS project (ANR 2009) intends to realize the coherent receiver part on silicon photonic, ULTIMATE focus on the transmitter side. ULTIMATE project will bring a competitive advantage to the partners of this project and especially Alcatel-Lucent in a highly competitive market where technological differentiators are required.