The energy dissipation and fault rates in future CMOS integration are expected to require the abandonment of traditional system reliability in favour of approaches that control errors across the application, runtime support, and system architecture. Commercial stakeholders of stream processing applications, such as multimedia analysis & retrieval and webpage ranking systems, already feel the strain of inadequate system-level scaling and robustness under increasing user demand. While such applications can tolerate certain imprecision (errors) in their calculations, this aspect is currently not used for system scalability and resilience. The ESP-SD project will derive theory, methods, and a prototype set of tools for scalable adjustment of computation and error-propagation in stream processing applications operating under a fault-generating computing environment. This will be achieved via the following innovations: * stochastic models of error tolerance in algorithms for multimedia and linked-data analytics (used in audio/video matching, semantic multimedia retrieval, webpage ranking systems, etc.); * new forms of accelerated error-tolerant computation within numerical stream processing libraries; * opportunistic designs for compiler and runtime support offering graceful resilience to runtime errors. ESP-SD aims for up to two orders of magnitude of throughput and energy scaling against conventional processing (under the same platform), with application results that are reliable in a stochastic sense. That is, all mechanisms for acceleration, energy saving and reliability in ESP-SD are geared towards minimizing the "expected" error in applications, and not the worst-case error. The project will derive practical designs demonstrating its impact, examples of which are provided in the "Impact Summary" and the "Pathways to Impact" on JeS.

Today's portable microelectronic systems, such as mobile telephones, require high energy efficiencies to further battery life. They also require compact electronics. Combining these two requirements poses a problem with relation to their power supplies, since it implies greater miniaturisation, high conversion efficiencies and high power densities. Using silicon-based DC/DC converters places limits on how far these improvements can go. We intend to make use of a new gallium-nitride transistor technology to develop smaller, more efficient power supplies. Specifically, we will produce a 10W power supply in this new technology, with a high voltage conversion factor, and integrate it inside a contemporary microelectronics package. The only way that this will work is to operate the new power supply at incredibly high switching frequencies (>100 MHz), which is 10-100 times faster than today's power supplies. The project then revolves around solving the challenges of: 1) how to operate such a power supply at very high frequencies; 2) how to integrate it into a small, modern, microelectronics package. We expect key challenges to be the creation of unacceptable electromagnetic emissions from the high switching speeds, and the need to accurately control the impedances of the circuit, since circuit impedances become more significant the faster one switches. We will solve the challenges by deploying an advanced version of a drive-pulse shaping technique that we call "pulse quietening", and by using modern integration techniques, including the creation of a custom chip to control the new power supply. Our method is to create several prototypes, running at increasingly high speeds, from 1MHz up to 100 MHz. We will create models and theories about the most efficient way to drive the power supply transistors and measure the outputs, as well as furthering our knowledge and application of pulse quietening.

Modern wireless communications rapidly approach the verge of the spectrum availability and new disruptive technologies are urgently needed to meet the projected capabilities and demands for efficiency and privacy of 5G communications and beyond. We will exercise an original holistic design approach to build and test novel integrated digital/RF wireless architectures exploiting the full potential of unconventional degrees of freedom and enabling dramatically increased information capacity in small-cell networks. Our cross-disciplinary studies will inform and influence future wireless technologies, help address the societal demand for 'green' and intelligent communications, and create a body of scholarship to promote the UK's unique blend of innovative engineering, free spirit of entrepreneurialism and educational rigour.

The computational demands of modern computer applications make the pursuit of high performance more critical than ever, and mobile, battery-powered devices, as well as concerns related to climate change, require high performance to co-exist with energy-efficiency. Due to physical limits, the traditional means for improving hardware performance by increasing processor frequency now carries an unacceptably high energy cost. Advances in processor fabrication technology instead allow the construction of many-core processors, where hundreds or thousands of processing elements are placed on a single chip, promising high performance and energy-efficiency through sheer volume of processing elements. Many-core devices are present in practically all consumer devices, including smartphones and tablets. As a result, the general public in developed countries interact with many-core software daily. Many-core technology is also used to accelerate safety-critical software in domains such as medical imaging and autonomous vehicle navigation. It is thus important that many-core software should be reliable. This requires reliable software from programmers, but also a reliable "stack" to support this software, including compilers that allow software to execute on many-core devices, and the many-core devices themselves. Recent work on formal verification and testing by myself and other researchers has identified serious technical problems spanning the many-core stack. These problems undermine confidence in applications of many-core technology: defective many-core software could risk fatal accidents in critical domains, and impact negatively on users in other important application areas. My long-term vision is that the reliability of many-core programming can be transformed through breakthroughs in programming language specification, formal verification and test case generation, enabling automated tools to assist programmers and platform vendors in constructing reliable many-core applications and language implementations. The aim of this five-year Fellowship is to undertake foundational research to investigate a number of open problems whose solution is key to enabling this long-term vision. First, I seek to investigate whether it is possible to precisely express the intricacies of many-core programming language using formal mathematics, providing a rigorous basis on which software and language implementations can be constructed. Second, I aim to tackle several open problems that stand in the way of effective formal verification of many-core software, which would allow developers to obtain strong guarantees that such software will operate as required. Third, I will investigate raising this level of rigour beyond many-core languages. A growing trend is for applications to be written in relatively simple, high-level representations, and then automatically translated into high-performance many-core code. This translation process must preserve the meaning of programs; I will investigate methods for formally certifying that it does. Fourth, I will formulate new methods for testing many-core language implementations, exploiting the rigorous language definitions brought by my approach to enable high test coverage of subtle language features. Collectively, progress on these problems promises to enable a *high-assurance* many-core stack. I will demonstrate one instance of such a stack for the industry-standard OpenCL language and the PENCIL high-level language, showing that high-level PENCIL programs can be reliably compiled into rigorously-defined OpenCL, integrated with verified library components, and deployed on thoroughly tested implementations from many-core vendors. Partnership with four leading many-core technology vendors, AMD, ARM, Imagination Technologies and NVIDIA, provides excellent opportunities for the advances the Fellowship makes to have broad industrial impact.

POETS (Partially Ordered Event Triggered Systems) is a significantly different way of approaching large, compute intensive problems. The evolution of traditional computer technology has taken us from simple machines with a handful of bytes of memory and (by the standards of today) glacial clock speeds, to multi-gigabyte architectures running five or six orders of magnitude faster, but with the same fundamental process at the heart: a central core doing one thing at a time. Over the past few years, architectures have appeared containing multiple cores, but exploiting these efficiently in the general case remains a 'holy grail' of computer science. POETS takes an alternative approach, made possible only today by the proliferation of cheap, small cores and massive reconfigurable platforms. A previous EPSRC project, BIMPA, enabled us to assemble a million core machine, creating a kind of 'meta-computer'. Rather than program explicitly the behaviour of each core and each communication between them, as is done in conventional supercomputers, here the programmer defines a set of relatively small, simple behaviours for the set of cores, and leaves them to get on with it - with the right behavioural definitions , the system 'self-organises' to produce the desired results. BIMPA was designed primarily for neuroscience applications, but a subsidiary research objective allowed us to study the use of the architecture for alternative (physics-based) problems, and we have demonstrated that this kind of approach can lead to dramatic speed increases over conventional solution techniques. POETS is not a general-purpose computing technique, but it is elegantly suited to a variety of traditionally compute intensive engineering and research problems, where it can produce results orders of magnitude faster than conventional machines at a fraction of the cost. The purpose of this research project is to explore this application arena: what kind of architectures are best (fastest)? How might they be automatically configured to self-organise? How might we build bridges between this new technology and a nascent user base? Industry has invested heavily - quite sensibly - in computing technology over the years, and if POETS is to become the disruptive technology we believe it to be capable of, we need to address a serious 'hearts and minds' issue for commercial uptake to ensue.