Ubiquitous, high-performance communication is the backbone of our society, and promises to play an increasing role not only in individual's daily lives, but just as importantly in the background with communication among devices (e.g. vehicle-to-infrastructure for mobility, process control and monitoring in industrial and manufacturing, virtualization of full environments for the metaverse, among others). The resulting explosion in data that must be processed and communicated requires extraordinary bandwidth and network ubiquity, which in turn demands supporting electronics that is high performance, power efficient, and low cost. This EPSRC - NSF proposal targets a great leap forward in the most critical link, the wireless power amplifier, that is essential to realizing a vision of ubiquitous, high-speed, transparent mobile communication. Power amplifiers are among the most critical elements in any communication system as they dictates the overall efficiency of the system. GaN-based HEMTs are especially promising for high-performance power amplifiers, but current GaN-based systems suffer from limited frequency coverage, efficiency and linearity due to a combination of factors, including device design e.g. use of field plates effectively limits operation to 30 GHz and below, and materials issues e.g. deep level traps, self-heating means that gain and efficiency degrade rapidly both with output power as well as frequency. We leverage in this programme transformative advances in both GaN-based transistor design and novel circuit topologies to dramatically improve the efficiency, bandwidth, linearity, and cost of the key wireless elements of a communication system, through co-design. The technology is based on polarization-engineeered graded channel GaN HEMTs that show a substantial improvement in linearity in comparison to conventional HEMTs. By combining with thorough investigation of their underlying device physics including trap states and thermal management, we address major effects that degrade the performance of GaN at increasing frequencies (i.e. Ka band up to 40 GHz) by optimizing device design and fabrication. We will design harmonically terminated amplifiers based on our new class of contiguous modes, that allow designers wider choice of impedances for desired characteristics of efficiency, linearity and output power. The project brings together world leading experts in the Universities of Notre Dame, Bristol and Sheffield, working alongside supporting industry in UK and US, that completes the entire supply chain from substrate growers, device/chip fabrication to circuit designer in both countries. The targeted enabling millimetre-wave communication technology is expected to be the next frontier in emerging applications that play a critical role in the levelling up agenda to drive prosperity in all regions of the UK, the US and worldwide. For example 5G is expected to underpin new industries worth $13.2T in goods and services in the UK alone by 2035.

The ever-increasing combined carbon footprint of information and communications technology (ICT) is unsustainable - more efficient devices must be developed. Thermal characterisation, which feeds into design optimisation, is one of the key steps for ensuring the efficiency and reliable operation of the new electronic devices being developed. However, accurately measuring the temperature of leading-edge electronic devices is becoming increasingly difficult or impossible because of their small size, and that is the challenge addressed in this proposal. Wide bandgap electronic devices including GaN have great proven potential for the next generation of sustainable ICT and power electronics, contributing to the needed carbon emissions reduction. Miniaturization is one of the routes to further increase the efficiency and performance of wide bandgap electronic devices, decreasing the active region size to <200 nm, similar to the technology pathway that silicon (Si) electronics has taken, using concepts such as the FinFET. Thermal management, which is the efficient extraction of waste heat from the active part of the device, is especially important for achieving efficient reliable nanoscale electronic devices; thermal resistance increases as they are "scaled" to nanometre dimensions because of a thermal conductivity reduction and heat confinement in 3-D device structures, e.g. in a fin shape. While self-heating can be mitigated reasonably easily for lower power density Si FinFETs, it is potentially a significant roadblock for "scaled" wide bandgap devices which operate at enormous power densities. However there is currently no thermal imaging technique with a sufficiently high spatial resolution (e.g. Raman thermography has a diffraction limited resolution of about 0.5 micrometer, >10x the hotspot size) to be able to accurately measure the hotspot temperature of these novel nanoscale wide bandgap electronic devices. Instead we currently rely on complex electrothermal models to estimate the temperature of nanoscale devices, with inherent uncertainties - measurement is needed. A step change is required, namely a sub diffraction limit (super resolution) thermal imaging technique, which is addressed by the Future thermal Imaging with Nanometre Enhanced Resolution (FINER) project. We will develop a transformative nano quantum dot based thermal imaging (nQTI) technique to deliver nanometre resolution thermal imaging for the first time. To demonstrate the newly developed technique our application focus is on scaled wide bandgap electronic devices supplied by our national and international partners, however this technique will be widely applicable. Quantum dots are ideal for this application: They can be deposited as a nm-thickness film on the surface of the device being tested, and the emission colour is temperature dependent, which is what we exploit for thermal imaging. Structured Illumination Microscopy (SIM) and Stimulated Emission Depletion (STED) super-resolution techniques which were originally developed for fluorescence microscopy, but are presently unsuitable for thermal imaging, will be exploited to achieve a resolution as small as 50nm for nQTI. nQTI will enable nano-scale electrothermal models to be developed and experimentally verified. Accurate models will further our understanding of nano-scale self-heating and heat diffusion, feeding back into improved device designs and novel thermal management solutions. This work will be done at the Centre for Device Thermography and Reliability (CDTR) which has an international reputation for being at the forefront of high spatial and temporal resolution thermal imaging, pioneering Raman thermography. This expertise makes the CDTR ideally placed to deliver this project successfully. The generous industrial support for this programme demonstrates that there is a great need for this and their belief in our ability to successfully deliver it.

TOPIC: "Semiconductors" are often synonymous with "Silicon Chips". After all Silicon supported computing technologies in the 20th century. But Silicon is reaching fundamental limits and already many of the technologies we now take for granted are only possible because of Compound Semiconductors (CS). These technologies include The Internet, Smart Phones, GPS and Energy efficient LED lighting! CSs are also at the heart of most of the new technologies expected in the next few years including 5G wireless, ultra-high speed optical fibre connectivity, LIDAR for autonomous vehicles, high voltage switching for electric vehicles, the IoT and high capacity data storage. To date CSs are made in relatively small quantities using fairly bespoke manufacturing and manufacturers have had to put together functions by assembling discrete devices. But this is expensive and for many of the new applications integration is needed along the lines of the Silicon Integrated Chip. CDT research will involve: the science of large scale CS manufacturing (e.g. materials combinations to minimise wafer bow, new fabrication processes for non-flat surfaces); manufacturing integrated CS on Silicon and in applying the manufacturing approaches of Silicon to CS. The latter includes using generic processes and generic building blocks and applying statistical process control. By applying these approaches students will address and invent new ways to exploit the highly advantageous electronic, magnetic, optical and power handling properties of CSs and generate novel integrated functionality for sensing, data processing and communication. NEED: This CDT is a critical part of the strategic development of a CS Cluster supporting activity throughout the UK. It is part of the development of a wider training portfolio including apprenticeships and CPD activities, to train and upskill the CS workforce. Evidence of the critical need for a CDT, has been identified in a survey and analysis conducted by UK Electronics Skills Foundation highlighting the specific skills required in this rapidly growing high technology industrial sector. "We are looking for PhD level skills plus industry experience. We don't have the time to train up new staff." "There are no 'perfect employees' for CS companies, as this is effectively a new area. Staff, including those with PhDs, either have silicon skills and need CS-specific training, or have CS skills and need training in volume tools and processes, either in the cleanroom or in packaging." - quotes from CS Skills Survey - Report UKESF July 2018. We have worked with the CSA Catapult utilising the skills need they have identified as well as companies across the spectrum of CS activities and are confident of the absorptive capacity: the expected PhD level jobs increase for the existing cluster companies alone would employ all the students and the CDT will support many more companies and academic institutions. APPROACH: a 1+3 programme where Year 1 is based in Cardiff, with provision via taught lectures using university approved level 7 modules and transferable skills training, hands on and in-depth practical training and workshop material supplied by University and Industry Partner staff. A dedicated nursery clean room to allow rapid practical progress, learning from peer group activity and then an industry facing environment with co-location with industry staff and manufacturing scale equipment, where they will learn the future CS manufacturing skills. This will maximise cross fertilisation of ideas, techniques and approach and maximise the potential for exploitation. Y2-Y4 consist of an in depth PhD project, co-created with industry and hosted at one of the 4 universities, and specialised whole cohort training and events, including communication, responsible innovation, entrepreneurship, co-innovation techniques and innovative outreach.