AlGaN/GaN high electron mobility transistors (HEMTs) are a key enabling technology for future power conditioning applications in the low carbon economy, and for high efficiency military and civilian microwave systems. GaN-on-Si is highly attractive as a low cost, medium performance technology platform which has been proved to be usable even up to the W-band. The main down-sides of Si are the low bandgap and hence resistive lossy substrate especially at modest elevated temperatures, the vulnerability of the Si to unintentional doping with gallium during epitaxy causing RF losses, and the somewhat restricted power handling resulting from the relatively low thermal conductivity of the Si compared to the 4" SiC growth substrates currently used. However the cost benefits are dramatic allowing 6" or even 8" high volume wafer processing. 6" GaN-on-Si epitaxy is already available driven by the emerging GaN-on-Si power switch market, however it is optimised for high voltage, switched-mode operation. Improved RF power amplifier (PA) efficiency using GaN-on-Si, which is the focus of this proposal, would reduce the transistor temperature rise, reduce the substrate losses and deliver a low-cost high-performance technology as it would reduce the transistor temperature rise and reduce the substrate losses. The advance that is required is an optimised RF specific GaN-on-Si transistor architecture, which requires detailed understanding of electronic traps introduced into the GaN buffer of these devices by iron, carbon and carbon/iron co-doping, which is presently lacking. The key aim of this proposal is to control and model the device capacitances and conductances using novel epitaxial design of the GaN buffer, as this is key to delivering improved efficiency, gain and linearity in RF amplifiers.

Abstracts are not currently available in GtR for all funded research. This is normally because the abstract was not required at the time of proposal submission, but may be because it included sensitive information such as personal details.

The evolution of silicon technology since the 1960's has focussed on doubling performance and functionality every 18-24 months through miniaturization. Critical dimensions measured in tens of nanometres are now common place and billions of components connected by miles of wiring can be packed onto a wafer no larger than a thumb nail. Today the focus is shifting away from more scaling (called more Moore after the founder of Intel, Gordon Moore) towards increasing functionality through the introduction of mixed technologies on silicon (called more than Moore). This project investigates the incorporation of ultra thin ferroelectric materials into silicon nanoelectronics and two of its many applications.Capacitance is the rate of change of charge with voltage. It is the defining property of capacitors which are necessary in many electronic systems but are relatively large. Ferroelectrics can shrink capacitors by three orders of magnitude, because their electric permittivity is so high. More than that, their capacitance can be made to vary depending on the applied voltage so very small and tunable capacitors can be made, which can find applications in hand held electronics products in order to reduce power consumption. If they could be integrated onto a silicon microchip there would be further space savings. Thin layers are expected to produce even higher capacitance. However there is evidence that capacitance starts to reduce below 50 nm as dead layers are said to form near the interface with electrodes, but this may be an interface effect which can be lessened through engineering. Recently there has been experimental evidence that effective negative capacitance can be seen in ultra-thin ferroelectric films. If such material can be incorporated into a transistor then it would be able to reduce the voltage needed to switch a transistor between its on and off states (the sub-threshold slope). This would transform silicon technology, allowing a new generation of more powerful single core processors. Modern computers have dual or multi-core processors. A single core processor would generate too much heat but is still desirable for many applications. Capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switch off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. Integrating a ferroelectric film with negative capacitance into the gate of a transistor would reduce the overall capacitance and thus the sub-threshold swing. The need to understand and produce high quality ferroelectric ultra-thin films is imperative for each of these applications. Atomic Layer Deposition (ALD) at Newcastle and Pulsed Laser Deposition (PLD) at Imperial College will be used to deposit thin films of the ferroelectric materials barium titanate (BTO) and barium strontium titanate (BST). Both allow deposition thicknesses with atomic level precision. Extensive characterisation is needed to assess quality of these ferroelectric films. First principles computer simulation will be used to gain a better understanding of the films and to direct experiments. The deposition and thermal parameter space will be mapped to identify best ferroelectric properties for given constraints laid down by the silicon fabrication. Transistors will be made incorporating the best ferroelectric films to confirm the reduction in sub-threshold slope. Ferroelectric capacitors integrated onto silicon will be demonstrated, quantifying the capacitance increase per unit area and examining the fabrication constraints needed to maintain high transistor performance. This will also help identify integration issues, which also include equipment contamination and the development of ferroelectric etches.

There is a strong need for a new network to consolidate electronics research in UK universities. In recent years there have been major changes in technology, as the push for miniaturization has led to components with characteristics far from ideal transistor switches interconnected by wires instantaneously. Today's transistors get too hot, leak current, vary in size and are produced in their billions on chips the size of a thumb nail interconnected relatively slowly by miles of wiring. This creates a formidable challenge for designers, who already face the complexity of design on a bewildering scale. The public have an appetite for all things electronic and demand new and better products year on year. This also creates a challenge for designers and an opportunity for the electronics community. By working together these challenges can be tackled, making the UK's electronics community fit for purpose in the coming years to face critical challenges at the interface between design and technology. Complementing industry facing groups such as the National Microelectronics Institute (NMI) and the Electronics Knowledge Transfer Network (EKTN), the network will form part of a highly visible coordinated alliance to government and the media, who can use it for information, opinion and clarification in this space. This is important for the UK economy as the global electronics market is worth more than a trillion dollars annually. The initial membership will be drawn from the technology community who formed the Si Futures network and those participating in the design Common Vision. Together they represent a significant proportion of the UK academic community. There is a recognition that a broader electronics research community than those included in the previous network grants need to come together.

POETS (Partially Ordered Event Triggered Systems) is a significantly different way of approaching large, compute intensive problems. The evolution of traditional computer technology has taken us from simple machines with a handful of bytes of memory and (by the standards of today) glacial clock speeds, to multi-gigabyte architectures running five or six orders of magnitude faster, but with the same fundamental process at the heart: a central core doing one thing at a time. Over the past few years, architectures have appeared containing multiple cores, but exploiting these efficiently in the general case remains a 'holy grail' of computer science. POETS takes an alternative approach, made possible only today by the proliferation of cheap, small cores and massive reconfigurable platforms. A previous EPSRC project, BIMPA, enabled us to assemble a million core machine, creating a kind of 'meta-computer'. Rather than program explicitly the behaviour of each core and each communication between them, as is done in conventional supercomputers, here the programmer defines a set of relatively small, simple behaviours for the set of cores, and leaves them to get on with it - with the right behavioural definitions , the system 'self-organises' to produce the desired results. BIMPA was designed primarily for neuroscience applications, but a subsidiary research objective allowed us to study the use of the architecture for alternative (physics-based) problems, and we have demonstrated that this kind of approach can lead to dramatic speed increases over conventional solution techniques. POETS is not a general-purpose computing technique, but it is elegantly suited to a variety of traditionally compute intensive engineering and research problems, where it can produce results orders of magnitude faster than conventional machines at a fraction of the cost. The purpose of this research project is to explore this application arena: what kind of architectures are best (fastest)? How might they be automatically configured to self-organise? How might we build bridges between this new technology and a nascent user base? Industry has invested heavily - quite sensibly - in computing technology over the years, and if POETS is to become the disruptive technology we believe it to be capable of, we need to address a serious 'hearts and minds' issue for commercial uptake to ensue.