Computing pervades our lives, impacting our health, work, entertainment and social interaction. Over recent years, the technology inside the devices providing these services has undergone a radical change: where once, processing was undertaken by relatively homogeneous "sequential" devices, in which essentially one thing happened at a time, the new systems compose a range of specialized devices, some targeting specific problem sub domains, and almost all exhibiting considerable "parallelism", where many things can happen at the same time. This is true on all scales, from the internals of a mobile phone, to the massive data centres which serve web applications such as Google. This poses a substantial challenge for the software industry: writing correct and efficient programs for heterogeneous, highly parallel systems is much harder than for current technologies and most developers lack the skills and training to write safe and efficient code. Faced with this difficulty, software developers will often avoid writing parallel code completely, or else will use inappropriate, non-scalable and error-prone approaches based on explicit threads of program execution. Given the hardware trend towards increasingly complex, increasing parallel (manycore) systems, this is an inherently short-term strategy that is doomed to failure, Our project addresses this issue. Our key insight is that humans in general, are very good at using patterns to understand, predict and act in the real world. This insight translates into the world of software engineering in general, and parallel heterogeneous programming in particular. Our work will help programmers to recognize patterns in pre-existing and new applications, and to transform these pattern occurrences into forms which allow them to be exploited, adapted and run effectively on the new hardware platforms. The systems we develop will work in partnership with software developers, reducing the complexity of the task, automating and semi-automating the development task. The result will help the industry to develop new applications, and to update existing applications, with less effort, fewer errors and better resilience as the underlying technology continues to evolve.

Users want mobile devices that appear fast and responsive, but at the same time have long lasting batteries and do not overheat. Achieving both of these at once is difficult. The workloads employed to evaluate mobile optimisations are rarely representative of real mobile applications and are oblivious to user perception, focussing only on performance. As a result hardware and software designers' decisions do not respect the user's Quality of Experience (QoE). The device either runs faster than necessary for optimal QoE, wasting energy, or the device runs too slowly, spoiling QoE. SUMMER will develop the first framework to record, replay, and analyse mobile workloads that represent and measure real user experience. Our work will expose for the first time the real Pareto trade-off between the user's QoE and energy consumption. The results of this project will permit others, from computer architects up to library developers, to make their design decisions with QoE as their optimisation target. To show the power of this new approach, we will design the first energy efficient operating system scheduler for heterogeneous mobile processors which takes QoE into account. With heterogeneous mobile processors just now entering the market, a scheduler able to use them optimally is urgently needed. We expect our scheduler to be at least 50% more energy efficient on average than the standard Linux scheduler on an ARM BIG.LITTLE system.

We live in an era of multi-cores: computing processors are no longer marketed by their clock speeds, they are marked by the number of cores. The fundamental limits of energy and power density of processors will soon push us further into an age of dark-silicon where only a small portion of the chip can be powered at any time. In such a setting, putting more of the same processing cores on a chip (i.e. homogeneity) gives no advantage. This has forced computer architects to introduce heterogeneous many-core systems built around distinct processors -- which have different energy and performance characteristics and each is specialised for a certain class of applications. Computer architects now hope that software will find ways to unlock the potential of heterogeneous many-cores. Software developers, however, are struggling to cope with this dramatic increase in complexity; and the current compiler tools, whose role is to enable software makes effective use of the underlying hardware, are simply inadequate to the task. It is already a daunting task to build optimising compilers for homogeneous multi-cores consisting of identical cores, even just targeting performance (i.e. to make programs faster). It typically takes several generations of a compiler to start to effectively exploit the processor's potential, by which time a new processor appears and the process starts again. It will be a fundamentally more difficult task to design efficient compiler heuristics for optimising energy (i.e. to reduce energy consumption) and performance on heterogeneous many-cores, especially given the subtle interactions of different cores and inter-connections. Even if successfully achieved, the task of compiler design must likely to be started again when moving to a new released processor. This never ending game of catch-up inevitably delays time to market, meaning that we rarely fully exploit the hardware in its lifetime. If no solution is found, we will be faced with software stagnation and will be unable to offer scalable computing performance -- a driving force that has dramatically changed our society over the past 50 years. What is needed is an approach that evolves and adapts to the future hardware architectural change and delivers scalable performance over hardware generations. This project offers precisely that. It will achieve this by bringing together two distinct areas of computer science: parallel compiler design and machine learning to develop a new paradigm for energy and performance optimisation. Our key insight is that the best optimisation strategies can be learned from similar software/hardware settings; and the learnt knowledge can be constantly refreshed without human involvement. This project will deliver such a smart, adaptive compilation system. We will use machine learning to acquire knowledge of workloads, applications and the underlying hardware, testing new compilation strategies, learning how each individual program should be optimised for each specific computing environment, and constantly improving the optimisation heuristics over time. As knowledge of the application environment grows, our system will make programs faster and more energy efficient; for example, software will respond quicker and the battery life will last longer on mobile phones. It will reduce time to market for software products and deliver scalable performance as hardware advances. If successful, such as programme of work will help to the looming software crisis of dark silicon, which will be of benefit to academics and UK industry, and system software researchers and developers worldwide.

The worldwide software market, estimated at $250 billion per annum, faces a disruptive challenge unprecedented since its inception: for performance and energy reasons, parallelism and heterogeneity now pervade every layer of the computing systems infrastructure, from the internals of commodity processors (manycore), through small scale systems (GPGPUs and other accelerators) and on to globally distributed systems (web, cloud). This pervasive parallelism renders the hierarchies, interfaces and methodologies of the sequential era unviable. Heterogeneous parallel hardware requires new methods of compilation for new programming languages supported by new system development strategies. Parallel systems, from nano to global, create difficult new challenges for modelling, simulation, testing and verification. This poses a set of urgent interconnected problems of enormous significance, impacting and disrupting all research and industrial sectors which rely upon computing technology. Our CDT will generate a stream of more than 50 experts, prepared to address these challenges by taking up key roles in academic and industrial research and development labs, working to shape the future of the industry. The research resources and industrial connections available to our CDT make us uniquely well placed within the UK to deliver on these aspirations. The "pervasive parallelism challenge" is to undertake the fundamental research and design required to transform methods and practice across all levels of the ICT infrastructure, in order to exploit these new technological opportunities. Doing so will allow us to raise the management of heterogeneous concurrency and parallelism from a niche activity in the care of experts, to a regularised component of the mainstream. This requires a steady flow of highly educated, highly skilled practitioners, with the ability to relate to opportunities at every level and to communicate effectively with specialists in related areas. These highly skilled graduates must not only have deep expertise in their own specialisms, but crucially, an awareness of relationships to the surrounding computational system. The need for fundamental work on heterogeneous parallelism is globally recognised by diverse interest groups. In the USA, reports undertaken by the Computing Community Consortium and the National Research Council recognise the paradigm shift needed for this technology to be incorporated into research and industry alike. Both these reports were used as fundamental arguments in initiating the call for proposals by the National Science Foundation (NSF) on Exploiting Parallelism and Scalability, in the context of the NSF's Advanced Computing Infrastructure: Vision and Strategic Plan which calls for fundamental research to answer the question of "how to enable the computational systems that will support emerging applications without the benefit of near-perfect performance scaling from hardware improvements." Similarly, the European Union has identified the need for new models of parallelism as part of its Digital Agenda. Under the agenda goals of Cloud Computing and Software and Services, parallelism plays a crucial role and the Commission asserts the need for a deeper understanding and new models of parallel computation that will enable future technology. Given the UK's global leadership status it is imperative that similar questions be posed and answered here.