The HPC Digital Autonomy with RISC-V in Europe (DARE) will invigorate the continent’s High Performance Computing ecosystem by bringing together the technology producers and consumers, developing a RISC-V ecosystem that supports the current and future computing needs, while at the same time enabling European Digital Autonomy. DARE takes a customer-first approach (HPC Centres & Industry) to guide the full stack research and development. DARE leverages a co-design software/hardware approach based on critical HPC applications identified by partners from research, academia, and industry to forge the resulting computing solutions. These computing solutions range from general purpose processors to several accelerators, all utilizing the RISC-V ecosystem and emerging chiplet ecosystem to reduce costs and enable scale. The DARE program defines the full lifecycle from requirements to deployment, with the computing solutions validated by hosting entities, providing the path for European technology from prototype to production systems. The six year time horizon is split into two phases, enabling a DARE plan of action and set of roadmaps to provide the essential ingredients to develop and procure EU Supercomputers in the third phase. DARE defines SMART KPIs for the hardware and software developments in each phase, which act as gateways to unlock the next phase of development. The DARE HPC roadmaps (a living document) are used by the DARE Collaboration Council to maximize exploitation and spillover across all European RISC-V projects. DARE addresses the European HPC market failure by including partners with different levels of HPC maturity with the goal of growing a vibrant European HPC supply chain. DARE Consortium partners have been selected based on the ability to contribute to the DARE value chain, from HPC Users, helping to define all the requirements, to all parts of the hardware development, software development, system integration and subsequent commercialization.

HPC Digital Autonomy with RISC-V in EurHPC Digital Autonomy with RISC-V in Europe (DARE) will address Europe’s deficit in digital autonomy for High Performance Computing and AI, by creating truly European products for European supercomputers for research and industry. The project builds upon the solid research foundation from EPI, EUPILOT, EUPEX, DEEP-SEA, eProcessor, MEEP and related projects, and it takes advantage of the open RISC-V ecosystem, chiplet revolution and open-source software. It is the first phase of the ambitious 6-year plan set out in the DARE FPA proposal, and it defines clear intra- and inter-phase SMART KPIs and success criteria, on the road to European digital autonomy while supporting current and future computing needs. We will develop and tape-out, in advanced technology, three RISC-V-based chiplets: a vector accelerator for high-precision HPC and emerging applications, an AI Processing Unit inference accelerator for HPC AI applications and an HPC-focused European general-purpose processor. These chiplets bring cost and yield advantages by going beyond the reticle size limitations imposed by monolithic chips and they will be integrated in a mix-and-match fashion to build specific systems. DARE uses a carefully selected set of the most significant European HPC and AI applications to drive hardware (HW) and software (SW) activities in a HW/SW co-design scheme, in order to ensure that the project’s HW and SW results meet the requirements of the European HPC and AI communities. It will build a complete SW stack, optimized for DARE HW, that supports these cutting-edge applications. To make rapid progress, SW and HW developments proceed in parallel, leveraging early access to RISC-V hardware emulation and simulation. Finally, the project will elaborate a detailed technical roadmap and pathfinding, defining the major steps and milestones to be followed in the next phase, in order to achieve the goal of next-generation post-exascale EU supercomputers.

For improving the capabilities of general-purpose AI models and for extending their applicability to domains where the temporal dimension – among several others – is of importance, we will target the development of the next generation of Multimodal Space-Time Foundation Models (MSTFMs). These will combine spatio-temporal understanding, which is important even for modalities such as the visual one that have already been introduced in large generative models, with the effective management of new time-relevant modalities that are yet to be supported in foundation models, such as industrial time series data, remote sensing data and health-related measurements. Real and synthetic data, to mitigate data scarcity, will be leveraged for training general-purpose MSTFMs and for further adapting them for specific downstream tasks. Real data used for training will include data directly provided by members of the consortium as well as data from relevant European Data Spaces, while complementary synthetic data will be generated by exploiting existing generative AI capabilities as well as new ones developed in the project. European HPC infrastructure is directly included in the consortium to ensure the availability of the necessary computing resources.