The EMINENT project is concerned with the following research areas: (i) emerging memory technologies (memristors and spintronic devices) used in a non-Von Neumann context, (ii) hardware implementations of bio-inspired neural networks (Spiking Neural Networks), (iii) hardware dependability (robustness, reliability and test) and design-for-dependability. The goal of the EMINENT project is to provide a dependable Emerging Memory-based Spiking Neural Network architecture. This goal will be achieved by fulfilling the following objectives: (i) study of meaningful dependability threats in SNN architectures, (ii) reliability estimation campaign; (iii) post-fabrication test strategy and design-for-test solutions; (iv) strategy for architecture dependability improvement.

Percutaneous medical procedures, guided imagery or not, benefited from the contributions of localization tools and navigation. However, these tools remain imperfect. In the context of percutaneous procedures using a needle, we demonstrate that we can provide the physician augmented interventional environment that will allow one hand, to answer to its problem of maximizing the benefit / risk ratio and other hand, to push its limits in making gestures that are not currently considered because of under-performing tools. Two major challenges must be addressed in designing the new generation of tools to support interventional radiological procedures. 1 / as the simplifying assumption of a linear model of needle can be a major source of imprecision, with a consequence of failures of interventional gesture, the new navigation systems must take into account real-time deformation of needle. 2 / the knowledge of these deformations and thus deviations from an ideal planed trajectory requires the development of new real-time correcting methods of trajectory of the needle. A consortium of experts was formed to address these challenges: TIMA (Techniques de l’Informatique et de la Micro-électronique pour l’Architecture des systèmes intégrés), which brings its expertise in micro-fabrication and micro-sensors, demonstrated the feasibility of a new way of understanding the deformations of a needle. 3S-R (Sols, Solides, Structures, Risques) brings to the consortium its expertise in the field of physical and mechanical behavior of materials for the optimum design and modeling applications. TIMC-IMAG (Techniques de l’Ingénierie Médicale et de la Complexité - Informatique, Mathématiques et Applications de Grenoble), which is specialized in navigation systems and Computer Assisted Medical Interventions, offers a new augmented navigated environment. The CIC-IT (Clinical Investigation Center - Technological Innovation) of Grenoble University Hospital brings its expertise in the field of innovative technology in Health to early and objectively estimate the Expected Medical Services associated with innovations developed in the project. Imactis, a startup in the field of interventional radiology, provides expertise in the industrialization of needle navigation systems. The federation of these experts in a single consortium can cover all specialties (medical, software, modeling, electronics, micro-system, control, mechanical, medico-legal) needed to meet the two previous challenges. At the end of this industrial research project, all technical and scientific evidence, as well as first demonstrators will be available to demonstrate the feasibility of the proposed approach. The stakes are perceived as highly strategic, especially in the field of interventional radiology. We believe that at least six major publications will be made by the consortium. Finally, the industrial transfer of these innovations will be facilitated by the partner Imactis, which will market the products of this work through its distribution network.

Secure circuits embed hardware primitives that provide security properties: Physical Unclonable Functions (PUFs) or attack sensors, for example. These only fulfil their role when powered, which makes a new class of attacks that would be carried out when the targeted circuit is powered off particularly worrying. The aim of our project is precisely to verify the feasibility of laser attacks on powered-off devices and to propose suitable countermeasures to protect against these attacks. In order to carry out this work, we first plan to design in-house and then have an external service provider manufacture a test circuit with carefully selected elementary blocks and simple security primitives for characterisation, testing and modelling purposes. We then plan to carry out laser injection campaigns on this circuit, but also on other circuits already available from the project partners. These experimental campaigns can therefore start at the beginning of the project. This first stage will lead to the development of a fault model, describing the observed faults as exhaustively as possible, at different levels of abstraction: physical, logical and functional. Once we understand the effects of laser attacks on powered-off devices, we plan to apply the resulting fault model to two classical examples of safety primitives. For the PUF, the aim will be to disprove the unclonability property, by experimentally modifying the statistical distribution of the identifiers generated by the PUF. This could go as far as gaining precise control of individual bits of the response obtained. The second application will be the deactivation of an attack sensor before its use, by exposing it to laser radiation when it is powered off. The aim here is to render the sensor non-functional once it is powered. Finally, we plan to illustrate the developed fault model by applying it to two existing systems, resulting from previous ANR projects, and which use the security primitives described above. Thus, we will first target the intellectual property protection system of the SALWARE project, protecting IP cores against illegal copying. This system is based on the intrinsic identification of the different instances of an IP core using a PUF, and the possibility of cloning the PUF would make it possible to illegally activate several components from a single legal activation. The second target device is an integrated substrate current sensor, known as BBICS, from the ANR LIESSE project. The objective here is to raise the detection threshold of the sensor to make it insensitive to the currents induced by a laser attack carried out later. Finally, once this original threat has been clearly identified and validated, we will propose countermeasures that are adapted and suitably designed.

The efficient exploitation by software developers of multi-core architectures is tricky, especially when the specificity of the machine is visible to the application software. To limit the dependencies to the architecture, the generally accepted vision of the parallelism assumes a coherent shared memory and a few, either point to point or collective, synchronization primitives. However, this requires to share information between may if not all the nodes. Unfortunately, as soon as the number of core is around 10 (ten), the communication cannot occur on a shared medium anymore, and designs make use of bus hierarchies or Networks on Chip. This latter solution is clean and efficient, but each core can see only the communications it is the target of, and unlike shared but, cannot spy what is going on between other cores. This is particularly difficult when implementing cache coherence and collective synchronizations, and a possible solution to overcome this issue is to use radio communications on chip. By nature, radio communications provide broadcast capabilities at negligible latency, they have thus the potential to disseminate information very quickly at the scale of a circuit and thus to be an opening for solving these issues. In the RAKES project, we intend to study how RF communication can solve the scalability of the above mentioned problems for architectures with a large number of cores (>256), by using mixed wired/RF NoC. We plan to study several alternatives and to provide (a) & virtual platform for evaluation of the solutions and (a) an actual implementation.

Most computations on real numbers manipulate them as floating-point numbers. State of the art processor architectures offer functional units supporting the half, single or double precision of the IEEE-754 standard [30]. These formats, of respectively 16, 32 or 64 bits, offer the equivalent of 3, 7 and 15 decimal digits. The reason for the two larger formats is not that programmers need that many digits on the output. Rather, they are useful to protect him from the accumulation and amplification of rounding errors in the intermediate computations. However, the programmer has to make a dramatic choice between these precisions, and then the chosen precision is unlikely to exactly match the needs of the application. At best, it will be overkill, meaning wasted time, memory and power in computing useless bits. At worst, it will be insufficient, meaning numerically wrong results, with possible catastrophic consequences in a world where embedded computing systems interfere more and more with our lives. Considering this, the main claim of this project is the following: accuracy should become a first-class concern in our computing ecosystems currently mainly focused on the cost-performance trade-off. This will lead to better quality numerical software, better trust in their results, but also better performance and power consumption when the accuracy needs are limited. The objective of this project is therefore to add accuracy considerations to cost/performance trade-offs, at all the levels of a computing system: 1. at the hardware level, with better support for lower-than-standard and higher-than-standard precisions, and with hardware support for adaptive precision; 2. at the level of run-time support software, in particular answering the memory management challenges entailed by adaptive precision; 3. at the lower level of mathematical libraries (for instance BLAS for linear algebra), enhancing well established libraries with precision and accuracy control; 4. at the higher level of mathematical libraries (which includes linear solvers such as LAPACK, ad hoc steppers for ordinary differential equations, triangularization problems in computational geometry, etc). This level is characterized by iterative methods where accuracy and precision control of the lower levels will enable higher-level properties such as convergence and stability; 5. at the compiler level, enhancing optimising compilers with novel optimisations related to precision and accuracy; 6. at the language level, embedding accuracy specification and control in existing languages, and possibly defining domain-specific languages with accuracy-aware semantics for some classes of applications. To achieve this goal, the project will focus on specific useful use cases in the domains of linear algebra, computational geometry, and machine learning. The main challenge to address in the lower levels is to offer precision control at an acceptable overhead. For this, the project can build upon the expertise of the project coordinator in hardware and software computing just right, on the expertise in processor integration at LETI, and on the compilation expertise at ENS. On the higher levels, the main challenge is to understand and formalize the accuracy requirements of a computation at each level. There is also a pervasive challenge of designing the relevant interfaces at each level for accuracy and precision control. Defining where the precision can be decided at compile-time, and where it has ti be decided at run-time, is also difficult. We claim that we can address this very difficult challenge for the considered use cases, thanks to the complementary application-domain experience of the project members. The project will develop a demonstrator based on a RISC-V system enhanced with variable-precision hardware, and an accuracy-aware software stack that covers all the levels above.