The HPC Digital Autonomy with RISC-V in Europe (DARE) will invigorate the continent’s High Performance Computing ecosystem by bringing together the technology producers and consumers, developing a RISC-V ecosystem that supports the current and future computing needs, while at the same time enabling European Digital Autonomy. DARE takes a customer-first approach (HPC Centres & Industry) to guide the full stack research and development. DARE leverages a co-design software/hardware approach based on critical HPC applications identified by partners from research, academia, and industry to forge the resulting computing solutions. These computing solutions range from general purpose processors to several accelerators, all utilizing the RISC-V ecosystem and emerging chiplet ecosystem to reduce costs and enable scale. The DARE program defines the full lifecycle from requirements to deployment, with the computing solutions validated by hosting entities, providing the path for European technology from prototype to production systems. The six year time horizon is split into two phases, enabling a DARE plan of action and set of roadmaps to provide the essential ingredients to develop and procure EU Supercomputers in the third phase. DARE defines SMART KPIs for the hardware and software developments in each phase, which act as gateways to unlock the next phase of development. The DARE HPC roadmaps (a living document) are used by the DARE Collaboration Council to maximize exploitation and spillover across all European RISC-V projects. DARE addresses the European HPC market failure by including partners with different levels of HPC maturity with the goal of growing a vibrant European HPC supply chain. DARE Consortium partners have been selected based on the ability to contribute to the DARE value chain, from HPC Users, helping to define all the requirements, to all parts of the hardware development, software development, system integration and subsequent commercialization.

The present proposal aims to realise an integrated pilot line focused on the developments of the wide–bandgap (WBG) semiconductors technologies for power and radio frequency (RF) electronics. The project will be realised by strengthening the existing facilities located in Finland, Italy, Poland, France, Austria, Germany and Sweden, and involving Universities and Research centres of the seven above-mentioned States operating in the field of advanced semiconductors and related technologies. The WBG semiconductor pilot lines will address all the front–end critical issues related to the realisation of devices with power and RF performance much higher than those realised by the conventional silicon technology, will define a clear roadmap for the development of such advanced technologies, will investigate strategies to improve the structural and electrical properties of WBG (and Ultra–WBG) semiconductors, and will develop new MEMS devices based on WBG and Ultra-WBG devices.

ViTFOX project develops a ferroelectric-augmented intelligent semiconductors technology to demonstrate a Vision Transformer (ViT) with superb energy efficiency of > 50 TOPS/Watt and make an impact on AI-powered edge applications. The project aims to strengthen the leading position of EU and Korea in Hafnia-based Si-compatible ferroelectric electronics pioneered in Europe (Germany) and significantly advanced by Korean researchers, members of this project. ViTFOX proposes advancements beyond the state of the art, at a TRL 4-5, in the whole value chain from materials and devices to heterogeneous and monolithic integration as well as design and simulation of the ViT circuits and systems. Three of the project objectives target the design and fabrication of the main components of the ViT, namely a Compute-in Memory demonstrator, a circuit level simulator and a hardware-software co-optimization platform with ferroelectric oxides. The platform will support two types of emerging memories, high-density 3D FeRAM developed in Korea and epitaxial Ferroelectric Tunnel Junctions developed in EU. Another set of objectives target the low voltage/low power operation of ferroelectric devices using epitaxial growth, new metal electrodes and advanced processing techniques such as atomic layer etching as well as the integration of these devices to fabricate memory arrays used in the ViT. The consortium consists of five Universities, two research organizations and one large European technology development laboratory, mobilizing all necessary expertise and infrastructure in ferroelectric and semiconductor technologies. The consortium plans to valorize the technology in two of the newly established Chips JU pilot lines on advanced integration during the project and advance it to higher TRL (> 5) after the project end to ensure manufacturability for future volume production.

Opto-electronic devices are opening exciting new applications everyday. With new display options using pliable substrates such as plastic and flexible glass, OLEDs manufacturers are bringing a wide range of new applications in lighting (e.g. energy efficient lighting) and different type of displays. Similarly, with the emergence of thin-film technologies in the solar cells market, new applications ranging from installations on curved surfaces to building-integrated PV has become possible. However, to meet the industry requirements for mass production, including low cost, manufacturing volumes and efficiency, many challenges still need to be addressed. These challenges for OPV, OLED and CIGs are scale-up from laboratory to mass production, selection of efficient manufacturing processes, employing inspection, control and measurement techniques to improve yield, quality and time-to-market. OLEDSOLAR aims to tackle these challenges by developinginnovative manufacturing processes for critical steps in the production of opto-electronic devices including OLEDs, OPVs and CIGs solar cells. The proposed activities include reconfigurable high yield (>10% improvement) processes to be scaled up, tested at pilot lines and implemented in production line for validation. A complete system of inspection, quality control, functional testing and measurements using advance system and sensors will be optimised in the project for efficient manufacturing of opto-electronics parts. Recycling and re-use strategies will be developed allowing resource efficiency and reduction of high value product wastes. Automation and advance processing software will be developed for overall control and monitoring of roll-to-roll (R2R) and sheet-to-sheet (S2S) manufacturing process. During 36 months, a multidisciplinary team of leading RTOs and industries in this field will dedicate their resources and effort to perform proposed activities in 8 WPs and guarantee the maximum impact of OLEDSOLAR project.

The goal of CITRES is to provide new energy storage devices with high power and energy density by developing novel multilayer ceramic capacitors (MLCCs) based on relaxor thin films (RTF). Energy storage units for energy autonomous sensor systems for the Internet of Things (IoT) must possess high power and energy density to allow quick charge/recharge and long-time energy supply. Current energy storage devices cannot meet those demands: Batteries have large capacity but long charging/discharging times due to slow chemical reactions and ion diffusion. Ceramic dielectric capacitors – being based on ionic and electronic polarisation mechanisms – can deliver and take up power quickly, but store much less energy due to low dielectric breakdown strength (DBS), high losses, and leakage currents. RTF are ideal candidates: (i) Thin film processing allows obtaining low porosity and defects, thus enhancing the DBS; (ii) slim polarisation hysteresis loops, intrinsic to relaxors, allow reducing the losses. High energy density can be achieved in RTF by maximising the polarisation and minimising the leakage currents. Both aspects are controlled by the amount, type and local distribution of chemical substituents in the RTF lattice, whereas the latter depends also on the chemistry of the electrode metal. In CITRES, we will identify the influence of substituents on electric polarisation from atomic to macroscopic scale by combining multiscale atomistic modelling with advanced structural, chemical and electrical characterizations on several length scales both in the RTF bulk and at interfaces with various electrodes. This will allow for the first time the design of energy storage properties of RTF by chemical substitution and electrode selection. The ground-breaking nature of CITRES resides in the design and realisation of RTF-based dielectric MLCCs with better energy storage performances than supercapacitors and batteries, thus enabling energy autonomy for IoT sensor systems.