The UDEC project aims at defining and developing an efficient and high performance universal channel decoder architecture model for emerging and future digital communication systems. In order to address the large variety of channel coding options and flavors specified in existing and coming digital communication standards, there is an increasing need for flexible solutions. However the need of optimal solutions in terms of performance, power consumption, and area still exist and cannot be neglected against flexibility. In common understanding, a “blind” approach towards flexibility results in some loss in optimality. The originality of UDEC project is related to unifying flexibility-oriented and optimization-oriented approaches. The main goal is to de deliver enablers and building block solutions in order to derive, for a specific application need, the best balance between a highly flexible solution and a specifically optimized one. From the technology point of view, channel decoder is one of the most computation, communication, and memory intensive, and thus, power-consuming component. A state of the art 2Mb/s 3G turbo decoder with ten turbo iterations must carry out more than 1.2 billion add-compare-select (ACS) operations per second, besides the additional overhead of data handling and control. Memory occupies more than 75% of the turbo decoder area, and extensive iterative data exchange and memories accesses are taken place until the convergence of the error correction process. Several powerful error correction techniques exist today, each suitable for specific application parameters (frame size, transmission channel, signal-to-noise ratio, bandwidth, etc). However, from the implementation point of view, only highly specialized solutions are available, each one supporting a single code. Considering the emerging multi-mode and multi-standard applications, as well as the increasing interest for Software Defined Radio (SDR) and Cognitive Radio (CR) concepts, combination of multiple error correction techniques becomes mandatory. As a matter of fact, a knowledge gap is growing quickly in the last few years between the need for flexibility in the digital base-band processing segment of modern communication systems, and the actual availability of flexible while efficient hardware support to the quest for reconfigurability. The main reason that determines this growing gap is related to the poor area and energy efficiency of flexible solutions proposed till now and the huge increase of non-recurrent engineering (NRE) costs in the production of dedicated integrated circuits for specific applications (ASIC) with new semiconductor technologies. The UDEC project intends to fill this gap in one of the most important area of digital communications, namely the field of forward error correction. Our approach in UDEC is based on application-specific architecture optimizations towards memory, power consumption, and flexibility issues. UDEC contribution is built around three main points: • Innovative universal channel decoder architecture design by means of deep and exhaustive analysis of modern channel decoding algorithms, architectures, and application requirements. • Memory, power consumption, and processing unit optimization as technique and technological building blocks of UDEC. • Validation, test, programming, and use of UDEC architecture and techniques in ASIC and FPGA target implementations. The required flexibility and performance will be addressed by leveraging a multiprocessor architecture with adequate processing units, interconnection network and a proper memory and power consumption optimization techniques. (1) Regarding the processing units, both ASIP and FPGA-based architectures will be considered and compared. (2) In the interconnect area, the results of the ANR AFANA project (Application-Field-Aware Adaptive Network-on-chip Architecture) will be considered as a possible solution, and will be evaluated on a power-consumption point of view. (3) Memory optimization techniques and technologies in the context of universal channel decoder will be addresses and novel memory schemes able to significantly reduce the storage overhead in parallel decoding architectures will be proposed. (4) Finally, power consumption reduction techniques will be proposed. Particularly, voltage/frequency “hopping” techniques developed in the LOMOSA Medea+ project by LETI will be evaluated as a possible solution to adapt power consumption to the needed performance requirement of the channel decoder for the ASIP solution. The project consortium will validate, assess, and demonstrate the efficiency of the proposed architecture model by real hardware implementation of a platform which efficiently supports all the coding techniques and parameters which are foreseen in WiMax/LTE standard (convolutional, LDPC, and turbo codes). The mentioned scientific advances together with the final demonstrated architecture will constitute a breakthrough in the design approach of channel decoders for digital communications. A key enabler and market driver of the designed decoder will be the compatibility with multiple existing FEC standards. Finally, it is important to note that UDEC will contribute significantly on preserving the France leadership in digital communication system design, and particularly in forward error correction, for both technologies and applications.
