The performance improvements obtained from the proper implementation of error control codes is one of the key elements that make the difference within competition. The key elements that makes a product successful can be either low complexity, low energy consumption, or low error probability performance. The three companies involved in the NAND project (STMicroelectronics, Thales and TurboConcept) are already present on several markets involving architecture of error control codes. The three companies are willing to exploit new disruptive technologies for commercial use of error control codes in both point to point and broadcast wireless communications. In parallel to these industrial needs, several scientists have recently tackled the performance evaluation of iterative decoders in stochastic architectures. In the next generation of integrated circuits with transistor sizes below 40 nm, every single gate may sometimes output a wrong value due to transient defects. One of the first proposed trends has been to evaluate, both theoretically and practically, the performance degradation induced by a stochastic architecture, then using wisely redundancy to reduce the negative effects introduced by the transistor noise. Through these research endeavors, an unexpected spin-off was identified: the noise inside the decoders is not necessarily an enemy to combat, but it can be used as an ally. Indeed, recent works have shown that the controlled injection of noise in an iterative error control decoder can significantly enhance the error correction performance, and thus, contribute to mitigate the effect of the transmission channel perturbations. In other words, and even if it may appear as a paradox at first glance, noise in an iterative decoder can help to combat channel noise! In this context, the NAND project will allow both academic and industrial partners to share a common objective: the design of high-performance and low-complexity error control codes that rely on this disruptive decoding technique in order to develop differentiated products and thus increase the French industry competitiveness. The consortium will analyze, both from theoretical and practical points of view, the performance gains that can be obtained from introducing some noise in iterative LDPC and Turbo decoders. The consortium targets significant performance gains, both in the convergence domain (a fraction of dB in Signal to Noise ratio) and in the error floor region (several orders of magnitude for a given Signal to Noise ratio). To carry out this project, all the aspects of the problem will be considered. From a theoretical point of view, the asymptotic performance of noisy decoders will be analyzed, in order to improve the performance in the convergence domain. The error floor performance analysis will consist on identifying the topological structures that might prevent the decoder to converge. We will study how noise can help iterative decoders to avoid this harmful topological structures. Fast simulation tools will be developed on parallel programmable architectures to confirm experimentally the theoretical analysis. Novel iterative decoder architectures will be proposed to take into account digital noise generation and injection in the decoding process. A more prospective analysis will be carried out for analog noise generation. As a proof of concept, two demonstrators (LDPC and Turbo-Code) will be implemented on FPGA boards. Finally, the NAND decoders will be incorporated into simulation chains, in order to measure their performance for non-Gaussian channels that are considered in several applications targeted by the three industrial partners (aeronautic mono-carrier channels, modulation with high number of states, fading channels, satellite channels with non-linear distortion).

Nowadays, the nanoelectronics market is dominated by mobile applications for which ultra-low operating power (LOP) devices are required. Hence, the research efforts are devoted not so much to increase the electrical performance of the single processor, which can be achieved by using an aggressive core parallelization, but rather to decrease the supply voltage VDD. Since the dynamic power consumption depends on VDD2, large benefits could be obtained by finding new device architectures and materials allowing circuits to work with reduced supply voltages. However, many technological and theoretical issues have to be addressed in order to open the way towards the design optimization of device architectures and materials for low-operating power applications. NOODLES goal is to develop predictive multi-scale simulations and efficient semi-analytical models ranging from full-quantum to semi-classical approaches, capable to identify the optimal choice of device architecture (nanowires, FinFETs, FDSOI), channel material (sSi, SiGe, III-V) and device operating principle (MOSFET, Tunnel-FET) in terms of the best electrical performance/consumption trade-off. In order to achieve this ambitious objective, NOODLES will explore the main physical mechanisms determining the properties of nanodevices for ultra-LOP applications. Such simulations have to be based on improved physical models able to reliably describe realistic devices. Therefore, NOODLES focus will be on the following problems: (i) the evaluation of self-heating effects and hot-carrier transport, which can be particularly detrimental in miniaturized nanostructures such as NWs, FinFETs and FDSOI; (ii) the realistic description of extra-channel parasitic effects such as access resistances and capacitances, which are as important as the channel region in determining the behavior of circuits based on short-channel devices, but have been neglected in most quantum simulations up to now; (iii) the assessment of III-V semiconductors as alternative materials to Si in both MOSFETs and Tunnel-FETs, which can indeed boost the electrical performance thanks to their high mobility and bandstructure properties. This project involves six partners who already worked together in a previous successful project founded by the ANR in 2010 (QUASANOVA). The partnership gathers the complementary expertise that is necessary to achieve NOODLES goals. In particular they have a strong track record in atomistic simulations of carrier transport, in 3D full-quantum self-consistent simulation of nanodevices, in advanced TCAD simulations and in analytical equations exploited to simulate benchmark circuits as the ring oscillator.

Bilinear pairings are special kinds of functions that map pairs of points on groups to points in a third group. They make it possible to design cryptographic schemes with new properties that seem to be difficult to achieve in a more traditional public key cryptography setting, such as cryptography without Public Key Infrastructure (PKI), shorter signatures, cryptosystems with additional properties, or more secure systems. The aim of the SIMPATIC (SIM and PAiring Theory for Information and Communications security) project is first to provide the most possible efficient and secure hardware/software implementation of a bilinear pairing in a SIM card. This implementation will be next used to improve and develop new cryptographic efficient algorithms and protocols in the context of mobile phone and SIM cards. These pairing-based cryptographic tools will be finally used to develop or improve the security of several mobile phone based services. The project will more precisely focus on e-ticketing and e-cash, on cloud storage and on the security of contactless and of remote payment systems.

Internet of Things (IoT) will play a major role in futuristic vehicle applications, such as vehicle-to-vehicle communications that reduce the chance of collision, advanced navigation systems that adjust the engine to features of the ground, predictive maintenance, partially autonomous vehicles, self-driving vehicles, etc. IoT relies on electronic systems that are capable of sensing, processing, and exchanging information. Guaranteeing the robustness, reliability, and maintainability of such electronic systems is a major challenge. The EDITSoC project addresses this challenge from the perspective of Electrical Diagnosis (ED). Efficient diagnosis is essential for shedding light into the failure mechanisms that occur in electronic systems so as to apply corrective actions to prevent failure re-occurrence and hence increase safety and reliability features. The aim of this project is to develop concepts, methodologies, and tools towards a complete system-level diagnosis. More specifically, given a System-on-Chip (SoC) that has failed, the objective of the project is to develop a unified diagnosis flow that first pinpoints the IP block (or an interconnection between IP blocks) that has failed (i.e. system-level diagnosis) and secondly, if the failure is attributed to an IP block, output a list of potential defects within the IP block and rank these defects according to their probability of occurrence (i.e. IP block-level diagnosis). Although the devised methodologies and tools can be used to diagnose SoCs that have failed during end-of-production test, the project mainly focuses on the diagnosis of SoCs that have failed during their mission mode, and for which a fast Failure Analysis (FA) is required and requested by the end-user in the context of customer returns. Two metrics will be used to quantify the success rate of the project, namely the (a) Diagnosis Cycle Time (DCT) which refers to the time required to complete the diagnosis, starting from the customer returns to the complete identification of the root cause of the failure(s), and (b) the Resolution Metric (RM) which refers to the total die area occupied by the defect candidates that the proposed diagnosis flow outputs. The DCT metric allows quantifying the resulting speed up of diagnosis, whereas the RM metric allows quantifying the improvement in distinguishability and number of defect candidates identified during diagnosis. The case studies used to validate the proposed solutions will be two large SoCs used in Advanced Driver Assistance Systems designed for automotive applications by STMicroelectronics in 55nm and 28nm technology nodes. More specifically, these SoCs target image recognition and treatment. They comprise heterogeneous digital and AMS IP blocks, including PLLs, ADCs, UARTs, I2C, SPI interfaces, Dual Data Rate 64bit controllers, parallel GPIO, Ethernet interface unit and on-chip processors. The use of two case studies is motivated by the need to show that the proposed diagnosis methodologies are technology independent.