The WAKEMEUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for the smart mobility and smart society domains. The already defined microcontrollers with 40nm embedded flash technology will be consolidated to build a solid manufacturing platform. Additional developments will be performed for the integration of memory, power management, connectivity, hard security on the same chip. The project will also target the industrialization of the embedded Phase Change Memory (PCM) technology built on top of the FDSOI 28nm logic process pilot line. The development of the ePCM will be driven by the final application requirements as well as decreasing the power consumption. The alternative memory solutions will be also studied as they have different - and complementary - traits in such areas as read/write speed, power and energy consumption, retention and endurance, and device density and benchmarked with the ePCM and the conventional eFlash. Continued advances in materials, device physics, architectures and design could further reduce the energy consumption of these memories. To achieve this goal of generating high value added semiconductor circuits in Europe in a breakthrough leading edge technology the project will deploy all the necessary activities to bring a new technology to an early industrial maturity stage. These activities encompass such developments as: technology enhancements for various specific application requirements such as wide temperature range and reliability, high security requests, high flexibility…, design enablment allowing first time silicon success, prototyping demonstrator products in the different application areas. In the WAKEMEUP project, new devices and systems will be developed by the application partners in automotive and secure based on FD-SOI and embedded digital technology to answer specific applications needs.

The objectives in Power2Power aim to foster a holistic, digitized pilot line approach by accelerating the transition of ideas to innovations in the Power Electronic Components and Systems domain. In the course of this project, the international leadership of the European industry in this segment will be strengthened by means of a digitized pilot line approach along the supply chain located entirely in Europe; working together with multiple organizations, combining different disciplines and knowledge areas in the heterogeneous power-ECS environment. Only these comprehensive efforts will allow reaching a high-volume production of smart power electronics to change the market towards energy-efficient applications to meet the carbon dioxide reduction goals of the European Union. Consequently, economic growth and Tackling grand societal challenges “Energy” and “Mobility” lead to safeguarding meaningful jobs for European citizens. Silicon-based power solutions will outperform new materials (SiC, GaN) for many more years in terms of cost-to-performance-ratio and reliability. Thus, the Silicon-based power solutions will keep innovating and growing the upcoming years. On a long run the project Power2Power will significantly impact the path to the industrial ambition of value creation by digitizing manufacturing and development in Europe. It fully supports this vision by addressing key topics of both pillars “Key Applications” and “Essential Capabilities”. By positioning Power2Power as innovation action, a clear focus on exploitation of the expected result is a primary goal. Smart energy utilization with highly efficient power semiconductor-based electronics is key in carefully utilizing the scarce resources. Energy generation, energy conversion and smart actors are these application domains where advanced high voltage power semiconductor components primarily impact the path toward winning innovations.

TA new generation of communications infrastructure is currently in development. The fifth generation (5G) communications technologies will provide internet access to a wide range of applications: from billions of low data rate sensors to high resolution video streaming. The 5G network is designed to scale across these different use cases and will use different radio access technologies for each use case. To support very high data rates 5G will use wide bandwidth spectrum allocation at mm-wave frequencies. The offered bandwidth at the mm-wave frequencies (above 24 GHz) is more than 10 times as large as that in the lower bands (sub 6 GHz). However, the move to mm-waves comes at a cost – increased path loss. This makes it extremely challenging to provide coverage at mm-wave frequencies. A partial remedy is to use beamforming to direct the radio energy to a specific user. For some deployment scenarios beamforming is not enough and the output power must also be increased. A major challenge is to bring affordable, high-performance mm-wave active antenna arrays into production. There is currently a market pull for this systems. The main objectives of the “5G_GaN2” proposal are substantial lowering the cost, power consumption and increase the output power of mm-wave active antenna systems. Advanced Gallium Nitride (GaN) technology will be used to get maximum output power and energy efficiency. High-volume and low-cost packaging and integration techniques developed for digital applications (CMOS) will be used. The capabilities of the developed technology will be shown in a set demonstrators. The application driven demonstrators will be used to guide the technology development towards maximum impact and exploitation in the post project phase. The consortium spans the complete value chain: from wafer suppliers, semiconductor fabrication and system integrators. In addition, key universities and research institutes guarantees academic excellence throughout the project.

The main objective of the storAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies, allowing the prototyping of high performance, Ultra low power and secured & safety System on Chip (SoC) solutions enabling competitive Artificial Intelligence (AI) for Edge applications. The main challenge addressed by the project is on one hand to handle the complexity of sub-28nm ‘more than moore’ technologies and to bring them up at a high maturity level and on the other hand to handle the design of complex SoCs for more intelligent, secure, flexible, low power consumption and cost effective. The project is targeting chipset and solutions with very efficient memories and high computing power targeting 10 Tops per Watt. The development of the most advanced automotive microcontrollers in FDSOI 28nm ePCM will be the support technology to demonstrate the high performances path as well as the robustness of the ePCM solution. The next generation of FDSOI ePCM will be main path for general purpose advanced microcontrollers usable for large volume Edge AI application in industrial and consumer markets with the best compromise on three requirements: performances, low power and adequate security. On top of the development and industrialization of silicon process lines and SoC design, storAIge will also address new design methodologies and tools to facilitate the exploitation of these advanced technology nodes, particularly for high performance microcontrollers having AI capabilities. Activities will be performed to setup robust and adequate Security and Safety level in the final applications, defining and implementing the good ‘mixture’ and tradeoff between HW and SW solutions to speed up adoption for large volume applications.

In a multi-disciplinary approach, FIXIT aims at the development of a disruptive, ferroelectric ultra-low power memory and computing technology, fostering the hardware implementation of novel AI-driven electronic systems. Ferroelectricity is the most energy-efficient non-volatile storage technology. FIXIT leverages two recent European discoveries of CMOS compatible ferroelectric materials: ferroelectric HfO2 as first reported in 2011 by NaMLab – the coordinator of FIXIT, and ferroelectric wurtzite AlScN discovered by the Project partner CAU in 2019. Our major goal is the scaling of ferroelectric synaptic devices to the <20nm regime while maintaining their analogue and multi-level switching properties. Moreover, we aim at the integration of these scaled devices into ultra-dense crossbar arrays featuring non-volatile multi-bit digital functionality and highly parallel multiply and accumulate operations, representing the synaptic interconnects calculation at the heart of AI-algorithms. In our consortium we build on the vast, interdisciplinary, and complementary expertise of the 11 project partners (3 industries, 1 SME, 4 universities, 3 RTOs) covering know-how on material, process and device development, CMOS integration, equipment and manufacturing, physical and electrical characterization, TCAD modelling, packaging, circuit design and system integration. Pushing European research in this topic will sustain the first-mover advantage and contribute to the European industry capability to provide advanced circuits for its needs. This is in-line with the European Chips Act, where the Commission has identified technological leadership in semiconductor technologies as indispensable for European digital sovereignty, and decided to support the field with large investments. FIXIT will also support Europe’s competitiveness in semiconductors with a systematic outreach to students, the training of young researchers and the building of international cooperation.