Moore's law states that, since their invention in 1947, every two years the number of transistors on an integrated circuit doubles. This is due to the shrinking of devices through advances in technology. However, as these devices are approaching the atomistic level, intrinsic variations are becoming more abundant, leading to a lower production yield and higher failure rates. In order to accommodate the increased variability of individual device characteristics there is a need for novel device architectures and circuit design methodologies. For example, Intel were forced to make the biggest change in transistor technology since the 1960s in order to reach the 45nm CMOS technology node. These predictions and issues were originally focussed on large-scale integration, mainly connected with microprocessor design. However, in the last 10 years the rise of Field Programmable devices (e.g. Field Programmable Gate Arrays - FPGA) both in terms of technology advances and application domains has meant that these issues are now relevant to these devices as well. Hence, the proposal focuses upon one of the current greatest challenges in electronic design: taking physical effects of intrinsic variability into account when the shrinking of device sizes approaches atomistic levels, in order to achieve functional circuit designs. Both process and substrate variations impose major challenges on the reliable fabrication of such small devices. These variations fall into two categories; deterministic variability, which can be accurately modelled and accounted for using specific design techniques, and stochastic variability, which can only be modelled statistically and is harder to overcome. The proposal will develop a reconfigurable design platform that can be manipulated at the device and digital abstraction levels in order to further understand and tackle the effects of stochastic variability in hardware upon next generation designs.The research proposal comprises four threads that build upon each other:- Design of a simulation model for a variability tolerant architecture, - Hardware realisation of this model,- Development of a comprehensive software framework, which will be able to interface the simulation model as well as the chip,- Development of bio-inspired approaches to tackle variability tolerant design. At its conclusion the project will have developed an understanding of how stochastic variability will affect circuit design in the future and will propose novel design methodologies to overcome stochastic variability. A novel, variability tolerant architecture will have been developed and realised as a simulation model and as a prototype in hardware. Both are vital steps towards next generation FPGA architectures.

Abstracts are not currently available in GtR for all funded research. This is normally because the abstract was not required at the time of proposal submission, but may be because it included sensitive information such as personal details.

Largely driven by material scientists, the flexible electronic research thus far has focussed on the materials and fabrication techniques. Whilst these are important areas, device modelling and circuit design is critical for taking the research closer to manufacturing. The acceptable degree of bendability for reliable operation of devices and circuits is a question that has not been addressed so far. This is a challenging because the standard transistor models for circuit simulation programs such as SPICE do not take into account the dynamic bendability induced effects. FLEXELDEMO will address these challenges by systematically characterizing the ultra-thin chips, identifying various parameters that change with bending, and suggesting improved BSIM models for devices over bendable substrates. This project has several anticipated benefits over a range of time-scales. In the short-term, this project will substantially improve our understanding of changes in various device parameters as a result of bending (uni-axial, bi-axial or twisting etc.), which has traditionally been under-studied. In the medium-term, it will enable designing of electronics on bendable substrate and predicting the behaviour of bendable electronics just like we do currently for planar electronics. In the long-term, the project will lead to intelligent use of bendability in improving circuit design. For example, location or shape dependent strain-field variations will be used to design location-/shape-aware circuits or to compensate electronic artefacts (e.g. self-calibration). The approach could also lead to design on bendable electronics based on ensemble of nanowires. Formulating the design rules and integration strategies through modelling will help in stabilizing the nascent flexible electronics technology. By adequately supporting the fabrication activities with modelling and simulation, this project will add significant new perspective to the fields of flexible electronics and electronics design.

The main goal of this project is to develop a fundamental understanding and applications of resistive switching in silicon-rich oxide. This may lead to a breakthrough in low-cost on-chip integration of Resistive Random Access Memory (RRAM) devices with Si microelectronics. To achieve that we will carry out detailed experimental studies of switching; develop a physical switching model; apply this model to design and fabricate demonstrator devices; characterise the devices, and develop circuit-level models for systems incorporating Si RRAM and hence extend the capabilities of Si microelectronics into new domains and applications. RRAM devices are components whose electrical resistance can be varied by applying an appropriate voltage. They are promising candidates for next generation electronic memories, offering a number of significant advantages over conventional Flash memory, including: very high packing density; fast switching; low energy switching; 3D integration to further increase memory capacity; ease of processing. Existing RRAM technologies are primarily based on metal oxide materials. However, Si- based devices have a number of advantages, including ease of integration with silicon CMOS processing technology, along with the possibility to tailor their electrical properties by varying programming voltage pulses. RRAM devices have potential applications beyond memory: if the device resistance can be continuously varied they may behave in a similar way to neurons, and may therefore be used in novel neural networks or other processing architectures. Also, as resistive switching shares many of the features of oxide failure in CMOS devices, the results from a study of RRAM will yield valuable information that may help reduce device failure, or even recovering damaged devices. We have recently developed a Si/SiO2 RRAM. Unlike competing technologies, it does not rely on the diffusion of metal ions, can be fabricated only from Si and SiO2, and operates in ambient conditions. Resistance contrast is up to 1,000,000, switching time <90ns, and switching energy 1pJ/bit or lower. Scanning Tunnelling Microscopy suggests individual switching elements as small as 10nm. Devices can be cycled thousands of times and can be operated in either unipolar or bipolar modes, with different characteristics in each: in the former, binary switching between discrete levels can be achieved, while in the latter we are able to continuously vary the device resistance, opening up the possibility of analogue devices such as memristors. Our devices are an alternative to existing metal oxide-based devices. The Si/SiO2 system is the building block of Si CMOS technology - our devices require no other material. We have found that the externally-set current compliance required for reliable resistive switching in metal oxide systems is not necessary in SiOx devices - asymmetric doping of the structure produces intrinsic self-limiting. In addition, the high degree of nonlinearity inherent in our semiconductor-based RRAM devices mitigates the problem of parasitic leakage currents in arrays of RRAM devices. Our project will go further than experimental studies of Si/SiO2 RRAM devices. We will also develop comprehensive theoretical models for the resistance switching process, and circuit-level models to investigate the application of our RRAM devices in real systems. Our approach is novel and unique in that it goes all the way from the atomistic modelling and electrical characterization of materials and fundamental electronic and ionic processes involved in resistive switching, through the simulation and fabrication of experimental devices to their optimisation and potential implementation in technology. This can only be achieved via synergy of expertise available at UCL and Glasgow.

Quantum technology gives the opportunity to open novel scientific and technological possibilities beyond the current physical and conceptual limitations. For example, an entirely new generation of electronic devices, which will allow technology to advance in the post-CMOS era, can be created. These devices will be based on quantum properties of electrons, such as tunnelling through barriers and spin, which will aim to progress in a range of applications from communications, quantum computing and quantum standard for electrical current to a wide spectrum of spintronics and molecular electronics. However, achieving this is challenging and requires developing novel theoretical methods and fabrication processes. This project aims to combine experiments and simulations to develop a suitable theory and methodology for simulating emerging quantum electronic devices. The main object of research in this proposal will be a single electron transistor (SET). In SETs it is possible to control, with very high precision, the electron flow through the device as individual charges. However, there are still numerous scientific and technical challenges to be overcome in order to create reliable and highly accurate SETs. This proposal aims to address some of these challenges and to answer a simple yet fundamental question: how do electrons flow through aggregates of atoms (quantum dots) in the context of a single electron transistor? The 'rules' for quantum transport in molecules and crystals with perfect symmetry are relatively well established and provide direction to the ongoing experimental effort. In contrast, a similar set of underpinning principles for quantum dots related to transport is clearly absent. A guiding principle in my work, which I follow here, is that theory and calculations should be used in synergy with experiments, addressing fundamental issues and providing insight that leads to improvement of the fabrication processes. This project brings together one UK company, the National Physical Laboratory and two research groups in the University of Glasgow to deliver progress in the field of improving the design parameters and performance of SETs.