WOOPTIX will upgrade to a 300mm field of view (FoV) metrology system a ready-to-market 50mm field of view Wooptix´s tool, based on a disruptive technology that measures the phase component of a beam of light (wavefront sensor) with a naked sensor, reaching a resolution orders of magnitude higher than other wavefront sensors. This technology has been patented by the company. The scalability of the solution will present an outstanding business opportunity for WOOPTIX leading the company to achieve an amazing turnover rise. Our semiconductor metrology system is capable of measuring the full 300mm silicon wafer geometry with a lateral resolution of 3.2µm and a height resolution of 0.3nm acquired in a single image snapshot in 100ms while capturing 15 million data points. The system works by using a standard digital image sensor to acquire the intensity of the reflected, non-coherent light from the silicon surface at two sperate locations along the optical path.

The objective of the 10ÅCe pThe objective of the 10ÅCe project is to explore and realize solutions for the 10Å CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The 10ÅCe project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: • Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. • Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: • Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. • Development of new computational lithography solutions to print 10Å CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: • Demonstrate a fully functional monolithic CFET (mCFET) • Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: • Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10Å 3D CFET devices, interconnect and materials