Quantum computation has just entered a new era, that of Noisy Intermediate-Scale Quantum (NISQ) technologies in which quantum processors are able to perform calculations beyond the capabilities of the world's greatest supercomputers. This remarkable achievement sets an important milestone in quantum computing (QC) and brings focus towards the ultimate goal of the QC roadmap: building a fault-tolerant quantum machine. A machine with sufficient error-free computing resources to run quantum algorithms with the potential to radically transform society. Algorithms that will help us better forecast weather and financial markets, speed up searches in unsorted databases, essential for the Big Data era, and most importantly, accelerate the pace of discovery of new materials and medicines, so relevant for the times we live in. The most promising routes to fault-tolerant QC will require quantum error correction (QEC) to enable accurate computing despite the intrinsically noisy nature of the individual quantum bits constituting the machine. The idea is based on distributing the logical information over a number of physical qubits. As long as the physical qubits satisfy a maximum error rate (1% for the most forgiving method, the surface code) fault-tolerance can be achieved. The exact physical qubit overhead (per logical qubit) depends on the error rate but considering state-of-the-art qubit fidelities, it will likely be a figure in excess of a hundred. QEC is then expected to take the number of required physical qubits to many thousands for economically significant algorithms and to many millions for some of the more demanding quantum computing applications. Scaling is hence a generic scientific and technological challenge. Building qubits based on the spin degree of freedom of individual electrons in silicon nanodevices offers numerous advantages over competing technologies such as the scalability of the most compact solid-state approach and the extensive industrial infrastructure of silicon transistor technology devoted to fabricating multi-billion-element integrated circuits. Besides, silicon electron spin qubits are one of the most coherent systems in nature, characteristic that has enabled demonstrating all the operational steps - initialization, control and readout - with sufficient level of precision for fault-tolerant computing. However, most of the results achieved so far come from devices fabricated in academic cleanrooms with relatively low level of reproducibility and in one- or two-qubit processors at best [Huang et al. Nature 569, 532]. But the recent demonstration of a single hole spin qubit [Maurand et al Nat Commun 7 13575] and electron spin control and readout in devices fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) platform open an opportunity to trigger a transition from lab-based proof-of-principle experiments to manufacturing qubits at scale [Gonzalez-Zalba et al, Physics World (2019)]. In the project SiFT, I will build on my pioneering work on CMOS-based quantum computing [Nat Commun 6 6084, Nat Elect 2 236, Nat Nano 14 437] to demonstrate, for the first time, all the necessary steps to run the surface code. I will target a two-dimensional qubit lattices where arbitrary quantum errors could be detected and corrected making clusters of qubits more reliable that the individual constituents. My quantum circuit designs will be manufactured in experimental and commercial silicon foundries that use very large-scale integration processes. The project will be the steppingstone towards building in the UK a large-scale silicon-based quantum processor with sufficient error-free computational resources to make an impact on society. It will help take QC beyond NISQ into the fault-tolerant era where the computational promises of QC can be fully exploited.

Modern society is becoming increasingly reliant on digital data, yet most data is stored on magnetic hard disk drives that consume large amounts of energy and are limited in reliability. As data centres and volumes of servers grow it is becoming necessary to explore more efficient future digital storage technologies. Domain wall (DW) memory is a type of solid-state magnetic random-access memory that controls the motion and position of magnetic domains along a nano-scale magnetic track, i.e., racetrack (RT) memory. The magnetic moments of DWs are driven by transferring spin angular momentum from electrons in an applied current pulse. The position of the DWs can also be controlled by including defects along the RT that hold the DWs in place between current pulses. Conventional RT memories can vastly improve their storage density and connectivity if they expand into three-dimensional (3D) RT systems. However, this makes their fabrication and understanding the behaviour of DWs very challenging due to reduced access. The aim of this project is to use advanced electron microscopy techniques to construct 3D RT memories that provide direct, nano-scale analysis of their chemistry, structure and DW motion under operando conditions (current pulsing and heating). This will allow effective engineering of their operation, taking the functional performance of 3D RTs into a brand-new realm of understanding. Through optimising the composition, geometrical design and current pulse parameters of the 3D RTs we can address the key issue of consistent, power-efficient control of DWs motion in complex 3D nanomagnetic arrays. The results will not only lead to high impact publications and conference presentations, but also provide a wealth of information for expanding the field of spintronics into advanced nanomagnetic systems with complex 3D geometries.

From an Information and Communication Technology (ICT) perspective, the 21st century is characterized by an explosion of requests for communication capabilities, high-performance computing, and cloud storage. Over the last few years, global Internet traffic has been growing exponentially. In this picture, transporting such an amount of data with existing electrical- interconnects and switching technologies will soon reach the "bottleneck" in terms of thermal loading, capacity, latency and power consumption. Optical- interconnects and switch fabrics combined with photonic integrated circuits (PICs) are seen as one of the most promising routes to push such limits. Silicon (Si) photonics is now considered as a reliable photonic integration platform. The beauty of Si Photonics stems from its ability to integrate microelectronics and photonics on a single Si chip utilizing standard CMOS IC technology. An important subset of this area is hetero-integration of III-Vs on Si, where the aim is the make use of III-V materials, with superior optical properties, to provide an efficient optical gain medium to circumvent the fundamental physical limitation of Si, i.e. Si cannot efficiently emit light, yet keeping the capability of light-routing, modulating, detecting and cost advantages of Si. In a breakthrough development, the investigators' group in UCL have shown that it is possible to grow epitaxially high-performance quantum dot (QD) lasers directly on Si substrates, opening up the possibility to monolithically integrate various types of III-V optoelectronic devices on Si. The pace of research on monolithic III-V/Si integration has then been dramatically accelerated and an increasing number of prestigious research groups including Bowers' group at UCSB and Arakawa's group at Tokyo University, and major Si chip companies, i.e. Intel, are currently devoting considerable programmes in this area. In addition to III-V/Si lasers, monolithic III-V/Si semiconductor optical amplifiers (SOAs) are also attracting significant interest as the key components for next-generation photonic integrated optical- interconnects and switching fabrics, as the application of SOAs is not limited only to compensate for loss and maintain signal levels as the signal propagates throughout a large number of optical components within the PICs, it is also used as a mature gating element for optical switches and has the advantages of ease of control, smaller footprint, low operating voltage, high ON/OFF extinction ratio, and fast transition times of the order of nanoseconds. However, such a III-V/Si SOA has not been developed to date. Building on the established expertise in monolithic III-V/Si QD lasers at UCL, this project proposal aims to develop the world's first monolithic III-V QD SOA on CMOS-compatible on-axis Si (001) substrates. In contrast to conventional native substrate based SOAs or III-V/Si SOAs using either flip-chip bonding or wafer bonding, the proposed method is fundamentally different, since the III-V SOAs will be integrated on Si by direct epitaxial methods, offering the possibility to achieve high-yield, low-cost and large-scale Si-based PICs, which is expected to be the technology platform to address next-generation optical- interconnect and switching solutions. With further development in Si photonics, i.e., providing the microelectronics world with the ultra-large-scale integration of photonic components, there will be scope to target applications in important areas such as consumer electronics, high-performance computing, medical and sensor solutions, and defence. This project will benefit from guidance from and joint work with both industrial as well as academic partners and will leverage major UK-based industrial and academic strengths in materials (e.g., CSC, EPSRC NEF) device processing (e.g., EPSRC CSHub, Glasgow) and photonics (e.g., Rockley, Lumentum), who are also well positioned to exploit this research.

The future of modern technology will be shaped by the ability to measure and control the electronic properties of functional materials. Transmission electron microscopy (TEM) has always been a key tool for materials development due to its ability to visualise internal structure and composition, and it is now able to resolve and measure individual atoms. However, measurement of functional properties (here, we are interested in internal electric fields) has been difficult; signals are relatively subtle. Until recently, the best method to directly measure internal fields was electron holography. This is not a straightforward technique, requiring a specialised microscope (with an electron biprism) and limitations on geometry, sensitivity and resolution that are all interlinked. However, this information is also present in scanning transmission electron microscopy (STEM) data, although it is not seen by conventional scintillator detectors. It is lost in the signal that they produce, which averages over the whole scattering pattern. New pixelated detectors that run at high speeds, capture every electron, and give several orders of magnitude more detail open the possibility to measure internal fields - and other properties - in a straightforward way. To access these signals, we will have to develop new methods to extract them from the large volumes data produced. There are many possible applications of techniques that we will develop. We will work with a range of partners who are developing materials from technologically important useful materials such as high-power semiconductors and light emitting devices, to fundamental questions about the way that ferroelectric materials can spontaneously generate and respond to internal electric fields.

The sensing, processing and transport of information is at the heart of modern life, as can be seen from the ubiquity of smart-phone usage on any street. From our interactions with the people who design, build and use the systems that make this possible, we have created a programme to make possible the first data interconnects, switches and sensors that use lasers monolithically integrated on silicon, offering the potential to transform Information and Communication Technology (ICT) by changing fundamentally the way in which data is sensed, transferred between and processed on silicon chips. The work builds on our demonstration of the first successful telecommunications wavelength lasers directly integrated on silicon substrates. The QUDOS Programme will enable the monolithic integration of all required optical functions on silicon and will have a similar transformative effect on ICT to that which the creation of silicon integrated electronic circuits had on electronics. This will come about through removing the need to assemble individual components, enabling vastly increased scale and functionality at greatly reduced cost.