The objective of the HOPE project is to propose a relevant solution for designing power efficient system on chip devices early in the design flow. On top of classical design flows, this high level approach relies on existing standards. Considering the large number of constraints, especially for performance and energy, designing battery-powered communicating mobile objects in an industrial context is a tough task. With the increasing number of embedded processing units (having high frequencies), the growing size of LCD touch screens or the different available sensors (i.e. camera) or radio interfaces, the energy consumption can rapidly exceeds a threshold unacceptable in regards to the capacity of embedded battery. Therefore, defining a hardware/software architecture that respects the required performance from the system application point of view and owns efficient power management strategies is a highly complex issue. This complexity has two main sources. The first main source of complexity is related to the intrinsic complexity of the communicating object itself. As an example, the Texas Instruments OMAP4 platform includes more than 300 IP blocks that need to be controlled (especially in energy), while the platform has to support the execution of an increasing number of applicative scenarios. For each scenario, a subset of components required for executing the scenario must be identified, as well as a power management strategy (e.g. V, F) for these components. Let us imagine that 50% of the processing power of a component is required for running a scenario. Should the clock frequency be decreased by 50%, or should the component be in idle/sleep mode for half the time? Note that thermal aspects as well as leakage currents must also be considered. For obvious cost reasons, it is moreover not possible to individually control each component (in V and F). So, an optimized partitioning of the system is required. The second main source of complexity is related the inefficiency of existing system level design tools to cope this complex issue. The identified solution must be consistent to support both the execution of applicative scenarios with their corresponding dynamism (including the embedded software) and a power management strategy. Verifying this consistency for the required level of performance is also a complex task. Finally, it is well known that the quality of the embedded software also has a non negligible impact on energy and temperature. So, being able to evaluate the efficiency of the software and identify optimization opportunities are key functionalities from a designer point of view. At micro architecture level, industrials have technologies and mature tools to model an architecture integrating common techniques used for power optimizations (e.g. power gating). The UPF (Unified Power Format - IEEE 1801) standard for instance defines primitives allowing designers to add power gating features on top of a functional RTL model. While essential at RTL level, this type of standard is not designed for a use at system level, so early in the design flow. The HOPE project intends to study and develop an approach for helping system level design and is based on the following main items: • An approach for sizing power architecture from a functional behavior analysis: break down the architecture in domains and define a power strategy (i.e. power intent); evaluate the solution in terms of power and temperature. • Study and develop SystemC-TLM models of components controlling power, clock and reset. Add power intent to purely functional SystemC-TLM models of a virtual platform. Verify functional/non-functional consistency and accurately evaluate the dynamic variation of the power consumption and the temperature. • Connect the developed models to an existing design flow with constraints vs. requirements tracking.

High Performance Computing (HPC) has become a major instrument for many scientific and industrial fields to generate new insights and product developments. There is a continuous demand for growing compute power, leading to a constant increase in system size and complexity. Efficiently utilizing the resources provided on Exascale systems will be a challenging task, potentially causing a large amount of underutilized resources and wasted energy. Parameters for adjusting the system to application requirements exist both on the hardware and on the system software level but are mostly unused today. Moreover, accelerators and co-processors offer a significant performance improvement at the cost of increased overhead, e.g., for data-transfers. While HPC applications are usually highly compute intensive, they also exhibit a large degree of dynamic behaviour, e.g., the alternation between communication phases and compute kernels. Manually detecting and leveraging this dynamism to improve energy-efficiency is a tedious task that is commonly neglected by developers. However, using an automatic optimization approach, application dynamism can be detected at design-time and used to generate optimized system configurations. A light-weight run-time system will then detect this dynamic behaviour in production and switch parameter configurations if beneficial for the performance and energy-efficiency of the application. The READEX project will develop an integrated tool-suite and the READEX Programming Paradigm to exploit application domain knowledge, together achieving an improvement in energy-efficiency of up to 22.5%. Driven by a consortium of European experts from academia, HPC resource providers, and industry, the READEX project will develop a tools-aided methodology to exploit the dynamic behaviour of applications to achieve improved energy-efficiency and performance. The developed tool-suite will be efficient and scalable to support current and future extreme scale systems.