This proposal is underpinned by our recent discoveries: out of plane ferroelectricity in hetero-bilayers of atomically thin body (ATB) semiconductors (Science, 2022); and realisation of wafer scale growth of a universal dielectric in the form of hexagonal boron nitride (h-BN) (Nature, 2022). The ground-breaking nature of the proposed work is in realisation of ultra-low power devices - namely ferroelectric field effect transistors (FeFETs) and tunnel electro-magneto-resistance (TEMR) devices - using industrially relevant complementary metal oxide semiconductor (CMOS) compatible processes that can perform both logic and memory functions to increase the energy efficiency of electronics. The carbon footprint (3% of total CO2 emission) of modern electronics is comparable to that of aviation and is expected to rise to ~10% by 2030 because of the von Neumann bottleneck where information is shuttled between the logic and memory devices, which increases energy consumption and reduces the processing speed. One objective of the proposed work is to directly explore and therefore understand the key processes that underpin the stable operation of FeFETs based on ATB semiconductors to significantly accelerate their development. Second objective is to integrate ferroelectric hetero- bilayers as tunnel layers between two ferromagnetic contacts to realise TEMR devices with magneto-resistance of > 1000%. The advantage of TEMR devices is that the tunnelling probability can be tuned with polarisation of the ferroelectric tunnel layer so that very large MR is achievable. In applications that are of strategic importance for the UK, energy efficient electronics are fundamentally important for meeting the net zero by 2050 goal as well as developing resilient local supply chain for semiconductors. We propose to focus on hetero-bilayers of transition metal dichalcogenide (TMD) compounds as a novel class of ferroelectric semiconductors where probing and understanding of device operation can rapidly improve the quality and control of available devices beyond the state-of-the-art, and for which recent work has highlighted significant application potential for high performance electronics. The motivation for such new devices is to address today's most important scientific challenges, namely that of climate change through energy efficient high-performance electronics. The recently published Nation Semiconductor Strategy highlights the need to develop the UK market and local supply chains. Atomically thin semiconductors were pioneered in the UK and this proposal will leverage the local expertise to develop new technology. Specifically, we aim to: (i) Develop methodology for realising ultra-clean semiconductor/dielectric interface using our recent breakthrough in high quality wafer scale chemical vapor deposition (CVD) grown h-BN (Nature, 2022) to eliminate hysteresis due to interface defects. We will also integrate our ultra-clean van der Waals (vdW) contacts on ATBs [enabled via EPSRC funded research (EP/T026200/1) and reported in Nature 2019, 2022] to eliminate defects at metal/semiconductor junctions. (ii) Establish a fundamental understanding of ferro-magnetic (FM) vdW contacts for spin injection and tunnelling behaviour through ATB TMD ferroelectric hetero-bilayers. (iii) Develop an integrated and scalable CMOS compatible fabrication process for ultra-low energy FeFETs and TEMR devices based on wafer scale CVD grown ATB hetero-bilayers using h-BN dielectrics and vdW contacts. (iv) Explore transport properties of FeFETs and TEMR devices that are capable of functioning as both logic and memory devices to establish understanding of fundamental operating mechanisms and energy footprint. Establish new design concepts exploiting the logic and memory functions of FeFETs and TEMR devices for high performance, low power electronics.

The high performance, at relatively low energy cost in today's field effect transistors (FETs), is achieved by decades long optimization of electrical contacts that has allowed the miniaturization of the semiconductor channel down to nanoscale dimensions. However, decreasing dimensions of the devices leads to power dissipation in the off state (leakage current) and other detrimental consequences that are collectively referred to as short channel effects. Emergent semiconductors, such as MoS2, that are naturally atomically thin can in principle mitigate several concerns related to short channel effects. In FETs with atomically thin body (ATB) channels, the charge carriers are confined within the sub 1nm thick semiconductor so that application of gate voltage influences all the carriers uniformly. This prevents leakage currents and allows the FETs to be sharply turned on or off. The fact that atomically thin individual layers of bulk-layered materials can be isolated necessitates the absence of dangling bonds in 2D semiconductors, which means that surface roughness effects are minimized. Recent research in FETs suggests that such ATB materials could be one pathway towards future energy efficient electronics that can operate down to milli volts using the current CMOS manufacturing platform. While the benefits of 2D semiconductor FETs in addressing short channel effects are obvious, they still possess lower performance compared to state-of-the-art silicon and III-V semiconductor analogues due the high contact resistance. To reap the benefits of ultra-short channel (sub 10 nm node) and tunnel FETs, contact resistances must be reduced down to the quantum limit. The contact resistance acts as a severe source-choke. This leads to degradation in the performance of the transistor, because the current depends very strongly on the effective gate voltage at the source injection point. The high contact resistance between metals and 2D semiconductors is a major barrier to their implementation in high performance short channel electronics. This proposal aims to pioneer low electrical resistance contacts on atomically thin body (ATB) transition metal dichalcogenide (TMD) semiconductors to enable the exploration of fundamental phenomena that is currently limited by poor contacts - with the motivation to understand key processes that underpin the behavior of short channel and tunnel field effect transistors so that devices with unprecedented energy efficiency and performance can be realized. The proposal builds on the our recent breakthrough on van der Waals contacts on ATB semiconductors published in Nature (April 2019) and strategic investments in the Materials for Energy-Efficient ICT theme at Cambridge through the Sir Henry Royce Institute. Our ambition is to realize low resistance contacts on ATB semiconductors that will allow a broad range of device communities to address and overcome the long-standing challenge of making good electrical contacts on low dimensional materials. The proposed work will underpin and impact ongoing programmes and initiatives aligned with several EPSRC priority areas. This includes adaptation of low resistance contacts for in operando characterization of battery materials using microelectrochemical cells and low resistance contacts for organic semiconductors and perovskites. This proposal aims to bring a step-change and establish an internationally leading programme in low resistance contacts for high-performance electronics based on ATB semiconductors that will add value and connect a broad range of communities. The proposed work will open up new pathways for achieving in-depth fundamental knowledge of physics of novel devices based on ATB materials to accelerate their development towards technological readiness and commercialization in higher value-added products.

In October 2014 the UK energy surplus during winter months dropped to below 5% overcapacity. In the future, this emergency overcapacity may be further diminished and actually become devastatingly insufficient, necessitating the national grid to divert large power demands to areas at opposite ends of the country or face serious and harmful disruption to energy supply. A viable solution to this supply problem is to build new national high voltage DC (HVDC) energy network connections in addition to more international connections to the super grid. To implement HVDC effectively, companies are considering two options: 1) to implement mature Si 300 MW HVDC technologies (circa 2009) requiring large overhead, land requirements, maintenance costs and cooling systems by scaling with the number of converters per line. Or 2) to invest in technologies which upscale the blocking voltage and the current capacity of individual power devices in a converter where fewer line converters and greater efficiency can be achieved for 2 GW MMC HVDC. Even by reducing the series chain effect in power transmission across the UK and conversion a 3% saving can equate to three 500 MW coal power stations from the current UK power usage of approximately 37 GW. This fellowship seeks to develop revolutionary Silicon Carbide (SiC) material for ultra-high voltage (UHV) >30 kV power devices with large current ratings, up to 150A, with the intention of pushing the current rating as far as possible. The current rating of UHV vertical devices depends on availability of large surface areas (> 1 cm2) and is presently limited due to defects from excess material deposits forming on the wafer during the material growth. This is a problem which I believe will be a critical roadblock to such technology and receives little attention as the proposed power ratings are currently off the 5-10 year power electronics roadmap. Problematically, many in the field trust it will be solved at that point, however, no major research drive is currently underway to solve this essential problem. Chemical vapour deposition (CVD) is the industry gold-standard technique for creating the semiconductor materials used in these UHV devices due to its excellent uniformity, scalability and reproducibility and so must be developed for quick uptake of any power device technology. For UHV devices the material choice and quality is key, where a defect free, thick (~100 um) layer with a large surface area is needed. Chlorinated chemistry is a recent development in SiC CVD and helps push growth rates up to 100 um/hr for thick layers and can be used to better achieve low background doping densities which are both required for high power technology. Here, thick high quality material will be achieved by state of the art epitaxial growth in the UK's only industrial SiC CVD at Warwick. In tandem to improving the material, its superiority will be shown by fabrication of vertical UHV devices: Schottky Diodes, PiN Diodes and MOSFETS, whilst developing IGBT processing, to show their potential for future modular multi-level converter (MMC) HVDC networks. Bipolar devices such as Si thyristors and Si PiN diodes will be used in rail traction and grid level HVDC applications due to the high quality of Si material which allows large current ratings. In 2014, Yole predicted that these sectors would boost the >3.3 kV SiC market and in 2015 Mitsubishi showed an all SiC 3.3 kV traction inverter system. I further predict that SiC devices will only completely replace Si IGBTs in the > 10 kV range when the current-limiting surface defects are minimised and device reliability due to minor material defects is better understood. Only then will large current ratings be achieved, which will allow the technology to surpass current HVDC technology. This fellowship directly studies these limiting mechanisms and will develop the material and associated technology to underpin this step change in power technology

The underlying remarkable material properties of diamond offer the prospect for semiconductor devices with extraordinary potential in high power applications, as well as those requiring operation at high temperature and in high radiation environments. However, despite their tremendous potential, the progress in developing diamond high voltage devices has been severely impeded by challenges associated with the availability of good quality substrates, limitations in thick and high quality epilayer growth and advanced device processing technologies . Moreover, advances have been additionally hampered by the lack of shallow n-type dopant species. However, recent progress by the applicants in developing diamond technologies make these above listed challenges considerably reduced enabling further advances in pursuit of developing high power diamond electronics. In this context, the applicants' recent discovery of the highly novel steady state deep-depletion concept for diamond devices opens routes for further advancements in the field of diamond power devices; critically, deep-depletion devices remove the need for an n-type doping. Vertical Deep-Depletion (D2) Diamond MOSFETs and Trench MOS Schottky barrier diodes (TMBS) will be realised offering exceptional performance in terms of power handling capability, size, switching frequency and thermal-radiation resilience. Developing more energy-efficient high-power devices will lead to efficient power converters, key for the drive to more efficient power generation and distribution systems within the context of the low carbon economy. However, additionally, diamond devices proposed will be that these devices can tolerate extreme operational environments and offer enormous potential in key sectors such as automotive, aerospace, and nuclear industrial sectors.