This proposal seeks funding to create a Centre for Doctoral Training (CDT) in Connected Electronic and Photonic Systems (CEPS). Photonics has moved from a niche industry to being embedded in the majority of deployed systems, ranging from sensing, biophotonics and advanced manufacturing, through communications from the chip-to-chip to transcontinental scale, to display technologies, bringing higher resolution, lower power operation and enabling new ways of human-machine interaction. These advances have set the scene for a major change in commercialisation activity where electronics photonics and wireless converge in a wide range of information, sensing, communications, manufacturing and personal healthcare systems. Currently manufactured systems are realised by combining separately developed photonics, electronic and wireless components. This approach is labour intensive and requires many electrical interconnects as well as optical alignment on the micron scale. Devices are optimised separately and then brought together to meet systems specifications. Such an approach, although it has delivered remarkable results, not least the communications systems upon which the internet depends, limits the benefits that could come from systems-led design and the development of technologies for seamless integration of electronic photonics and wireless systems. To realise such connected systems requires researchers who have not only deep understanding of their specialist area, but also an excellent understanding across the fields of electronic photonics and wireless hardware and software. This proposal seeks to meet this important need, building upon the uniqueness and extent of the UCL and Cambridge research, where research activities are already focussing on higher levels of electronic, photonic and wireless integration; the convergence of wireless and optical communication systems; combined quantum and classical communication systems; the application of THz and optical low-latency connections in data centres; techniques for the low-cost roll-out of optical fibre to replace the copper network; the substitution of many conventional lighting products with photonic light sources and extensive application of photonics in medical diagnostics and personalised medicine. Many of these activities will increasingly rely on more advanced systems integration, and so the proposed CDT includes experts in electronic circuits, wireless systems and software. By drawing these complementary activities together, and building upon initial work towards this goal carried out within our previously funded CDT in Integrated Photonic and Electronic Systems, it is proposed to develop an advanced training programme to equip the next generation of very high calibre doctoral students with the required technical expertise, responsible innovation (RI), commercial and business skills to enable the £90 billion annual turnover UK electronics and photonics industry to create the closely integrated systems of the future. The CEPS CDT will provide a wide range of methods for learning for research students, well beyond that conventionally available, so that they can gain the required skills. In addition to conventional lectures and seminars, for example, there will be bespoke experimental coursework activities, reading clubs, roadmapping activities, responsible innovation (RI) studies, secondments to companies and other research laboratories and business planning courses. Connecting electronic and photonic systems is likely to expand the range of applications into which these technologies are deployed in other key sectors of the economy, such as industrial manufacturing, consumer electronics, data processing, defence, energy, engineering, security and medicine. As a result, a key feature of the CDT will be a developed awareness in its student cohorts of the breadth of opportunity available and the confidence that they can make strong impact thereon.

Artificial neural networks have been shown to offer a powerful computing approach to encounter many classification problems as in synthetic vision (e.g. autonomous driving) and artificial intelligence (e.g. AlphaGo). While their implementations are often based on power-hungy CPU- and GPU-installations, first researchers have delivered initial application-specific solutions that demonstrate FPGAs to be a feasible and efficient alternative. This proposal aims at providing a generic reference implementation of ANNs on FPGAs that is tunable towards various application needs by parametrization. Since individual FPGA designs establish enormous costs of entry due to a higher engineering effort on a lower abstration level, an IP core that is available out of the box is a great R&D incentive that enables more researchers and engineers to embrace the emerging efficient heterogeneous computing more quickly and produce innovations and more compact and more efficient products on this basis. Besides this technological advance, this proposal enables a researcher with an enormous experience in mapping computations into FPGA hardware to make a valuable industrial experience in an international context with the major company in this domain. His expertise is ideally complemented with the application experience available at Xilinx who will benefit from opening a new growing market for manufactured FPGA devices. The development of the researcher's skill set is explictly addressed by complementing his academic background with industrial experience and scheduled cooperate trainings. As part of the dissemination activities, his network into the FPGA community is strengthened and approaches towards the ANN community are made.

Deep learning (DL) is the key technique in modern artificial intelligence (AI), which has provided state-of-the-art accuracy on many machine-learning based applications. Today, although most of the computational loads of DL systems are still spent running neural networks in data centres, the ubiquity of smartphones, and the upcoming availability of self-contained wearable devices for augmented reality (AR), virtual reality (VR) and autonomous robot systems are placing heavy demands on DL-inference hardware with high energy and computing efficiencies along with rapid development of DL techniques. Recently, we have witnessed a distinct evolution in the types of DL architecture, with more sophisticated network architectures proposed to improve edge AI inference. This includes dynamic network architectures that change with each new input in a data-dependent way, where inputs and internal states are not fixed. Such new architectural concepts in DL are likely to affect the type of hardware architectures that will be required to deliver such capabilities in the future. This project precisely addresses this challenge and proposes to design a flexible hardware architecture that enables adaptive support for a variety of DL algorithms on embedded devices. Primarily, to produce lower cost, lower power and higher processing efficiency DL-inference hardware that can be configured adaptably for dedicated application specifications and operating environments, this will require radical innovation in the optimisation of both the software and the hardware of current DL techniques. This work aims to perform fundamental research, development and practical demonstrator to enable general support for a variety of DL techniques on embedded edge devices with limited resource and latency budgets. Primarily, this requires radical innovation on the current DL architectures in terms of computing architecture, memory hierarchy and resource utilisation, as well as system latency and throughput: it is particularly important for the modern DL systems that the inference processes are dynamic, such as, the DL inference maybe input-dependent and resource-dependent. The proposal therefore seeks the following three thrusts: First, to build upon the existing work of the PI in optimising machine-learning models for resource-constrained embedded devices, towards achieving the goal that the network model could be dynamically optimised as needed through hardware-aware approximation techniques. Second, with newly-developed adaptive compute acceleration technology in programmable memory hierarchy and adaptive processing hardware, to seek a new ambitious direction to develop a set of context-aware hardware architectures to work closely with the approximation algorithms that can fully utilise the true hardware capabilities. Unlike traditional optimisation techniques for DL hardware inference engines, the proposed work will explore both software and hardware programmability of adaptive compute acceleration technology, in order to maximise the optimisation results for the target application scenarios. Third, this project will work closely with our industry and project partners to produce a practical demonstrator to showcase the effectiveness of the proposed DL framework versus traditional approaches, particularly, evaluating the effectiveness of the framework in real-world mission-critical applications.

Technology scaling has enabled fast advancement of computing architectures through high-density integration of components and cores, and the provision of systems on chip (SoC), e.g. NVIDIA Jetson, Xilinx UltraScale+ FPGA, ARM big.LITTLE. However, such systems are becoming hot and more prone to failure and timing violations as clock speed limits are reached. Therefore, parts of SoCs must be turned off to stay within thermal limits ("dark silicon"). This shifts challenges away from making designs smaller, setting the new focus on systems that are ultra-low power, resilient and autonomous in their adaptation to anomalies, faults, timing violations and performance degradation. There is a significant increase in numbers of temporary faults caused by radiation, and permanent faults due to manufacturing defects and stress. ITRS (https://irds.ieee.org/) estimates significant device failure rates, e.g. due to wear-out, in the short term. Hence, a critical requirement for such systems is to effectively perform detection and analysis at runtime, within a minimal area and power overhead. This is at odds with current state-of-the-art, including error correcting codes (ECC), built-in-self-test (BIST), localized fault detection, and traditional modular redundancy strategies (TMR), all resulting in prohibitively high system overheads and an inability to adapt, locate or predict faults. In complex living organisms, the nervous system is a much more efficient and adaptive "subsystem" that detects environmental changes and anomalies that impact them by transmitting signals between different parts of the organism. The nervous system works in tandem with the endocrine system, triggering appropriate regulatory or repair responses. Nervous systems naturally scale up, adapt and operate autonomously in a de-centralised manner. In NERVOUS our vision is to rejuvenate modern electronic systems and particularly the way in which such systems are designed to act autonomously to become more reliable. The goal of NERVOUS is to develop a methodology for "self-aware" electronic systems with an embedded artificial nervous system that can sense its state and performance, and exploit the structure and computational power of these kinds of bio-inspired mechanisms for autonomous tolerance of faults. NERVOUS is an inter-disciplinary collaboration that brings together networks of spiking neurons with electronic systems, so that they form hardware platforms with inherently embedded artificial "nervous systems". This approach has never before been used to make the technology we all carry around in our pockets more efficient and reliable, making NERVOUS "blue-skies" research at the cutting edge of bio-inspired electronic systems design. To ensure feasibility, NERVOUS's research programme is built around a number of hardware demonstrators of increasing complexity. NERVOUS is making use of state-of-the-art UltraScale+ FPGAs for rapid prototyping of nervous system components and complementing with an electronic design environment. To ensure accessibility beyond the project, NERVOUS will develop a design methodology and an EDA tool supporting automatic integration and training of NERVOUS components with traditional circuit designs, allowing engineers to apply our technology without having to worry about the intricate details of electronic-neuron interfacing. NERVOUS will demonstrate this for digital FPGA designs at the HDL level in collaboration with Xilinx. To ensure scalability, we will verify and evaluate the NERVOUS methodology on a range of relevant large-scale processor designs provided by our partner ARM, who will also advise on fault performance requirements. To ensure a route to industrial application and exploitation, we will demonstrate the NERVOUS methodology in the context of a real-word space application, e.g. space networking IP and modular spacecraft controller, through collaboration and secondments with our project partner TAS-UK.

There are increasing concerns about the safety and security of critical infrastructure such as nuclear power plants, the electricity grid and other utilities in the face of possible cyber attacks. As ageing controllers are replaced by smart devices based on Field-Programmable Gate Arrays (FPGAs) and embedded microprocessors, the safety of such devices raises many concerns. In particular, there is the very real risk of malicious functionality hidden in the silicon or in software binaries, dormant and waiting to be activated. Current hardware and software systems are of such complexity that it is impossible to discover such malicious code through testing. We aim to address this problem by closely connecting the system design specification with the actual implementation through the use of a formal design methodology based on type systems with static and dynamic type checking. The type system will be used as a formal language to encode the design specification so that the actual implementation will automatically be checked against the specification. Static type checking of data types and multiparty session types can ensure the correctness of the interaction between the components. However, as static checking assume full access to the design source code it cannot be used to protect against potential threads issuing from third-party functional blocks (know as ``Intellectual Property Cores'' or IP cores) that are commonly used in hardware design: the provider of the IP core can claim adherence to the types and protocols, so that the IP core will meet the compile-time requirements, but the run-time the behaviour cannot be controlled using static techniques. The same applies to third-party compiled software libraries. Therefore we propose to use run-time checking of data types as well as session types at the boundaries of untrusted modules ("Border Patrol"), so that any intentional or unintentional breach of the specification will safely be intercepted.