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ICT Integrated Circuit Testing GmbH

Country: Germany

ICT Integrated Circuit Testing GmbH

7 Projects, page 1 of 2
  • Funder: European Commission Project Code: 257379
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  • Funder: European Commission Project Code: 826589
    Overall Budget: 126,895,000 EURFunder Contribution: 29,382,500 EUR

    The metrology domain (which could be considered as the ‘eyes and ears’ for both R&D&I and production) is a key enabler for productivity enhancements in many industries across the electronic components and system (ECS) value chain and have to be an integral part of any Cyber Physical Systems (CPS) which consist of metrology equipment, virtual metrology or Industrial internet of things (IIoT) sensors, edge and high-performance computing (HPC). The requirements from the metrology is to support ALL process steps toward the final product. However, for any given ECS technology, there is a significant trade-off between the metrology sensitivity, precision and accuracy to its productivity. MADEin4 address this deficiency by focusing on two productivity boosters which are independent from the sensitivity, precision and accuracy requirements: • Productivity booster 1: High throughput, next generation metrology and inspection tools development for the nanoelectronics industry (all nodes down to 5nm). This booster will be developed by the metrology equipment’s manufacturers and demonstrated in an industry 4.0 pilot line at imec and address the ECS equipment, materials and manufacturing major challenges (MASP Chapter 15, major challenges 1 – 3). • Productivity booster 2: CPS development which combines Machine Learning (ML) of design (EDA) and metrology data for predictive diagnostics of the process and tools performances predictive diagnostics of the process and tools performances (predictive yield and tools performance). This booster will be developed and demonstrated in an industry 4.0 pilot line at imec, for the 5nm node, by the EDA, computing and metrology partners (MASP Chapter 15, major challenge 4). The same CPS concept will be demonstrated for the ‘digital industries’ two major challenges of the nanoelectronics (all nodes down to 5nm) and automotive end user’s partners (MASP Chapter 9, major challenges 1and 3).

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  • Funder: European Commission Project Code: 101194232
    Overall Budget: 111,474,000 EURFunder Contribution: 26,222,600 EUR

    The objective of the ACT10 project is to develop and demonstrate the required technology options, including their integration, for the 10Ångstrom node. The 32 participating partners cover a wide range of activities along the entire value chain for the manufacturing of CMOS chips. Activities include equipment development, computer aided design tooling and process technology development. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The project aims to enhance the attractiveness of the EU as a location for new cutting-edge high volume and legacy node fabs. The ACT10 project is built based on the following four pillars. 1. Lithography Equipment and Mask Technology: Increase key-performance indicators in the optical system of High-NA Lithography machines, along with developing advanced mask processes and equipment to reach optical imaging requirements, and nonlinear optics material lifetime effects. 2. Chip design and Block Level validation; Assessment of different CFET devices and evaluate building blocks for digital and analog IPs. 3. Process Technology: development of innovative solutions for routing of the stacked n- and p-devices of the CFET architecture, development of 0.55NA (high-NA) single patterning solutions, and the development of semi-damascene BEOL for the 10Å node. 4. Computational Metrology and Process Monitoring Equipment: develop computational metrology methods, and develop metrology and inspection modules and equipment.

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  • Funder: European Commission Project Code: 101111948
    Overall Budget: 108,925,000 EURFunder Contribution: 24,954,100 EUR

    The 14AMI project is about creating technological solutions for the 14 Angstrom CMOS technology node, including a fully integrated functional CFET (Complementary Field Effect Transistor) as new active CMOS device, and state-of-the-art holistic metrology techniques for both wafer and mask inspection and review. All is aimed to keep the pace in the industry to follow “Moore’s law”. The project addresses the following 3 main pillars that are relevant in enabling manufacture of 14A technology, 1) lithography, 2) metrology and 3) process module integration. In lithography the aim is to realize solutions for the 0.55NA EUV scanner platform to secure 14Angstrom node compliance in performance, that is, resolution, alignment, throughput and optics lifetime. In Metrology the objective is to cover wafer and mask metrology and quality control. The aim is to develop holistic metrology, tools & methods and data analytics to improve overlay, CD and focus measurement and quality control with a Precision to Tolerance, P/T, ratio between 0.1 and 0.3. In process module integration work covers the realization and demonstration of a CFET – Complementary Field Effect Transistor - CMOS device. Three options will be investigated for integration; a monolithic, sequential and a hybrid solution. In addition, the partners will develop a PFAS-free photo resist to reduce the ecological footprint of photolithography processes, and a smart AI based sensor technology to improve vacuum chambers' efficiency and reduce waste. At societal level the expected impact of the 14AMI project will support the partners and their supplier network to stay at the leading edge of high-tech developments, crucial to meet the digitization challenges of the European society. Moreover, 14AMI will “boost industrial competitiveness”, and attract talent in Europe, while enabling new application in areas such as security, communication and enabling of further automation in mobility, health and research.

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  • Funder: European Commission Project Code: 737479
    Overall Budget: 132,778,000 EURFunder Contribution: 28,340,000 EUR

    In line with industry needs, Moore’s law, scaling in ITRS 2013/2015, and ECSEL JU MASP 2016, the main objective of the TAKEMI5 project is to discover, develop and demonstrate lithographic, metrology, process and integration technologies enabling module integration for the 5 nm node. This is planned with available EUV/NA0.33 scanners that are optimized for mix and match with existing DUV/NA1.35 scanners, and with system design and development of a new hyper NA EUV lithography tool to enable more single exposure patterning at 5 nm to create complex integrated circuits. Process steps for modules in Front-end, Middle and Back-end of line are discovered and developed using the most advanced tool capabilities and they are evaluated morphologically and electrically using a relaxed test vehicle. During the development, specific challenges in metrology are assessed and metrology tools are upgraded or newly developed. The results are demonstrated in the imec pilot line with qualified metrology tools at the 5 nm node. The TAKEMI5 project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets, as set out in the MASP, at a (disruptive) new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the module integration of electronic devices for the 5nm node in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law which has celebrated its 50th anniversary. The cost aware development process supports the involved companies, and places them in an enhanced position for their worldwide competition. Through their worldwide affiliations, the impact of the TAKEMI5 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.

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