The objective of the 3DAM project is to develop a new generation of metrology and characterization tools and methodologies enabling the development of the next semiconductor technology nodes. As nano-electronics technology is moving beyond the boundaries of (strained) silicon in planar or finFETs, new 3D device architectures and new materials bring major metrology and characterization challenges which cannot be met by pushing the present techniques to their limits. 3DAM will be a path-finding project which supports and complements several existing and future ECSEL pilot-line projects and is linked to the MASP area 7.1 (subsection More Moore). Innovative demonstrators and methodologies will be built and evaluated within the themes of metrology and characterization of 3D device architectures and new materials, across the full IC manufacturing cycle from Front to Back-End-Of-Line. 3D structural metrology and defect analysis techniques will be developed and correlated to address challenges around 3D CD, strain and crystal defects at the nm scale. 3D compositional analysis and electrical properties will be investigated with special attention to interfaces, alloys and 2D materials. The project will develop new workflows combining different technologies for more reliable and faster results; fit for use in future semiconductor processes. The consortium includes major European semiconductor equipment companies in the area of metrology and characterization. The link to future needs of the industry, as well as critical evaluation of concepts and demonstrators, is ensured by the participation of IMEC and LETI. The project will directly increase the competitiveness of the strong Europe-based semiconductor Equipment industry. Closely connected European IC manufacturers will benefit by accelerated R&D and process ramp-up. The project will generate technologies essential for future semiconductor processes and for the applications enabled by the new technology nodes.

The overall objective of the IT2 project is to explore, develop and demonstrate technology options that are needed to realize 2nm CMOS logic technology extending the scaled Semiconductor technology roadmap to the next node in accordance to Moore’s law. These activities cover creation of Lithography equipment, new Processes & Modules and Metrology tools capable to create and deal with new 2nm node 3D structures, defect analysis, overlay and features. The topics addressed by the program relate to the ECSEL MASP 2019 Chapter 10; “Process Technology, Equipment, Materials and Manufacturing for electronic components and systems”, with emphasis on the following major challenge “the Extension of world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and “Developing Technology for heterogeneous System-on-Chip (SoC) Integration” of the ECSEL JU Annual Work Plan 2019. The relation of the IT2 project to world leadership regards the extension of the scaled semiconductor technology roadmaps and thereby maintain competence in advanced More Moore technology in Europe to support leading edge manufacturing. The relation of the IT2 project to the Developing Technology for heterogeneous System-on-chip Integration comes from activities regarding “System Scaling” in which technology is developed that enables wafer-to-wafer bonding creating 3D heterogeneous solutions with the aim to resolve performance limitations in power and data congestion. In regard to the annual work plan 2019, the IT2 project support the ECSEL JU objectives by contribution to the development of a strong and competitive Electronic Components and Systems (ECS) by involving many of the equipment and tool developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KLA along the value chain and knowledge institutes such as ARCNL, imec, PTB, TNO and TU/e. And by stimulating a dynamic ecosystem through through the involvement of SMEs like IBS, Recif, Reden and Unity.

The metrology domain (which could be considered as the ‘eyes and ears’ for both R&D&I and production) is a key enabler for productivity enhancements in many industries across the electronic components and system (ECS) value chain and have to be an integral part of any Cyber Physical Systems (CPS) which consist of metrology equipment, virtual metrology or Industrial internet of things (IIoT) sensors, edge and high-performance computing (HPC). The requirements from the metrology is to support ALL process steps toward the final product. However, for any given ECS technology, there is a significant trade-off between the metrology sensitivity, precision and accuracy to its productivity. MADEin4 address this deficiency by focusing on two productivity boosters which are independent from the sensitivity, precision and accuracy requirements: • Productivity booster 1: High throughput, next generation metrology and inspection tools development for the nanoelectronics industry (all nodes down to 5nm). This booster will be developed by the metrology equipment’s manufacturers and demonstrated in an industry 4.0 pilot line at imec and address the ECS equipment, materials and manufacturing major challenges (MASP Chapter 15, major challenges 1 – 3). • Productivity booster 2: CPS development which combines Machine Learning (ML) of design (EDA) and metrology data for predictive diagnostics of the process and tools performances predictive diagnostics of the process and tools performances (predictive yield and tools performance). This booster will be developed and demonstrated in an industry 4.0 pilot line at imec, for the 5nm node, by the EDA, computing and metrology partners (MASP Chapter 15, major challenge 4). The same CPS concept will be demonstrated for the ‘digital industries’ two major challenges of the nanoelectronics (all nodes down to 5nm) and automotive end user’s partners (MASP Chapter 9, major challenges 1and 3).

The objective of the ACT10 project is to develop and demonstrate the required technology options, including their integration, for the 10Ångstrom node. The 32 participating partners cover a wide range of activities along the entire value chain for the manufacturing of CMOS chips. Activities include equipment development, computer aided design tooling and process technology development. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The project aims to enhance the attractiveness of the EU as a location for new cutting-edge high volume and legacy node fabs. The ACT10 project is built based on the following four pillars. 1. Lithography Equipment and Mask Technology: Increase key-performance indicators in the optical system of High-NA Lithography machines, along with developing advanced mask processes and equipment to reach optical imaging requirements, and nonlinear optics material lifetime effects. 2. Chip design and Block Level validation; Assessment of different CFET devices and evaluate building blocks for digital and analog IPs. 3. Process Technology: development of innovative solutions for routing of the stacked n- and p-devices of the CFET architecture, development of 0.55NA (high-NA) single patterning solutions, and the development of semi-damascene BEOL for the 10Å node. 4. Computational Metrology and Process Monitoring Equipment: develop computational metrology methods, and develop metrology and inspection modules and equipment.