The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

FastLane targets a full, highly competitive and sustainable European value chain for Silicon Carbide (SiC) based power electronics. The goal is to provide a competitive technology excellence from engineered SiC substrates to novel devices, smart power modules and converters to broadened automotive and industrial applications. The next generation of SiC materials will be developed by improved quality of the crystalline starting material, material re-use and acceleration of substrate EU-based manufacturing. Based on the new materials the next generation SiC MOSFET power devices will be developed overcoming current limitations regarding efficiency, performance, robustness and sustainability and will integrate also new on-chip sensing technology. Power modules based on the devices will be further improved by several innovations, e.g. advanced sintering which will lead to improved power module reliability and therefore better sustainability. On component level, highly efficient and reliable inverters for automotive and industrial applications will be developed, including a variety of innovations in detail. In all steps, an improvement of SiC material characterization methodologies will increase the quality and the output of EU based semiconductors. Overall, performance and reliability are expected to increase greatly in all steps. These developments will lead to an overall reduction of cost and, by reduction of the footprint (lifetime increase, CO2 decrease, water consumption decrease), to a greener economy. With the envisioned goals, FastLane will decrease the environmental footprint all along the product lifecycle and contribute to the European Green Deal and ensure a sustainable European sovereignty in power electronics. Cost benefits for the end user will be achieved by the reuse of the automotive economy of scale. With these steps, FastLane contributes to the European societal goals and a greener economy.